AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 153

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

Figure 59. Data Transmission Format (CPHA = 0)
Figure 60. Data Transmission Format (CPHA = 1)
Figure 61. CPHA/SS Timing
Queuing transmission
7663E–8051–10/08
MOSI (from Master)
SCK Cycle Number
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 0)
SCK (CPOL = 1)
MISO (from Slave)
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
Capture Point
SPEN (Internal)
SS (to Slave)
Capture Point
SS (to Slave)
As shown in Figure 59, the first SCK edge is the MSB capture strobe. Therefore, the Slave must
begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start
the transmission. The SS pin must be toggled high and then low between each Byte transmitted
(Figure 61).
Figure 60 shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driv-
ing its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start
transmission signal. The SS pin can remain low between transmissions (Figure 61). This format
may be preferred in systems having only one Master and only one Slave driving the MISO data
line.
For an SPI configured in master or slave mode, a queued data byte must be transmit-
ted/received immediately after the previous transmission has completed.
MISO/MOSI
(CPHA = 0)
(CPHA = 1)
Master SS
Slave SS
Slave SS
MSB
MSB
MSB
1
MSB
1
2
bit6
bit6
2
bit6
Byte 1
bit6
3
bit5
bit5
3
bit5
bit5
bit4
4
bit4
bit4
4
bit4
Byte 2
bit3
bit3
5
bit3
bit3
5
6
bit2
bit2
6
bit2
bit2
Byte 3
7
bit1
bit1
7
bit1
bit1
LSB
8
LSB
LSB
8
LSB
AT89C51RE2
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