AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 157

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

Registers
Serial Peripheral
Control Register
(SPCON)
7663E–8051–10/08
Figure 65. SPI Interrupt Requests Generation
Three registers in the SPI module provide control, status and data storage functions. These reg-
isters are describe in the following paragraphs.
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•
•
•
•
•
Table 115 describes this register and explains the use of each bit
Table 115. SPCON Register
SPCON - Serial Peripheral Control Register (0D4H)
Bit Number
SPR2
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
7
7
6
5
4
SPEN
6
Bit Mnemonic
MODFIE
SPTEIE
MODF
SPTE
SPIF
SSDIS
MSTR
SPR2
SPEN
SSDIS
5
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and SPR0 for
detail).
Serial Peripheral Enable
Cleared to disable the SPI interface (internal reset of the SPI).
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit
has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request
is generated
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
MSTR
4
.
CPOL
3
CPHA
CPU Interrupt Request
2
SPI
AT89C51RE2
SPR1
1
SPR0
0
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