AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 42

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

42
AT89LP51RD2/ED2/ID2 Preliminary
Table 5-10.
Table 5-11.
• The /DPTR instructions provide support for the dual data pointer features described above
• The ASR M, LSL M, CLR M and MAC AB instructions are part of the Multiply-Accumulate
• The JMP @A+PC instruction supports localized jump tables without using a data pointer.
• The CJNE A, @R
• The BREAK instruction is used by the On-Chip Debug system. See
• Some third party assemblers/compilers do not support these instructions. In order to use
(See
Unit (See
them you may need to write assembly functions that emulate the instruction by declaring the
opcodes inline as shown in
Opcode
Opcode
A5 A4
A5 B6
A5 B7
A5 E0
A5 E4
A5 F0
A5 A3
A5 A4
A5 B6
A5 B7
A5 E0
A5 E4
A5 F0
A5 00
A5 03
A5 23
A5 73
A5 90
A5 93
Section
Section
AT89LP51RD2/ED2/ID2 Extended Instructions
Extended Instruction Assembly Emulations
Mnemonic
MAC AB
CJNE A, @R0, rel
CJNE A, @R1, rel
MOVX A, @/DPTR
CLR M
MOVX @/DPTR, A
Mnemonic
BREAK
ASR M
LSL M
JMP @A+PC
MOV /DPTR, #data16
MOVC A, @A+/DPTR
INC /DPTR
MAC AB
CJNE A, @R0, rel
CJNE A, @R1, rel
MOVX A, @/DPTR
CLR M
MOVX @/DPTR, A
5.4).
i
, rel instructions allow compares of array values with non-constant values.
5.3).
Table
5-11.
Description
Multiply and accumulate
Compare ACC to indirect RAM and
jump if not equal
Compare ACC to indirect RAM and
jump if not equal
Move external to ACC; 16-bit address
in alternate data pointer
Move ACC to external; 16-bit address
in alternate data pointer
Emulation
DB A5H, 00H
DB A5H, 03H or DB A5H followed by RR A
DB A5H, 23H or DB A5H followed by RL A
DB A5H, 73H or DB A5H followed by JMP @A+DPTR
DB A5H followed by MOV DPTR, #data16
DB A5H, A4H or DB A5H followed by MUL AB
DB A5H, E0H or DB A5H followed by MOVX A, @DPTR
DB E4H, E0H or DB A5H followed by CLR A
DB A5H, F0H or DB A5H followed by MOVX @DPTR, A
Clear M register
DB A5H, 93H or DB A5H followed by MOVC A, @A+DPTR
DB A5H, A3H or DB A5H followed by INC DPTR
DB A5H, B6H, (LABEL-$-3) where LABEL is the jump target
DB A5H, B7H, (LABEL-$-3) where LABEL is the jump target
Section 23. on page
Bytes
2
3
3
2
2
2
3714A–MICRO–7/11
Cycles
3/5
3/5
9
4
4
2
185.