AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 72

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

12.1.1
72
AT89LP51RD2/ED2/ID2 Preliminary
Quasi-bidirectional Output
.
Table 12-2.
.
Table 12-3.
.
Table 12-4.
Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi-
bidirectional port can be used both as an input and output without the need to reconfigure the
port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an
external device to pull the pin low. When the pin is driven low, it is driven strongly and able to
sink a large current. There are three pull-up transistors in the quasi-bidirectional output that
serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch for the
pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin
high if it is left floating. When the pin is pulled low externally this pull-up will always source some
current. The very weak pull-up is disabled when the port register contains a zero. In addition the
very weak pull-ups of all quasi-bidirectional ports can be disabled globally by setting the DPU bit
in the AUXR register (See
Register
PxM0.y
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
P4M0
P4M0
Port
0
0
1
1
0
1
2
3
4
Configuration Modes for Port x Pin y
Port Configuration Registers
Port Configuration Reset Values
Port Data
P4 (C0H)
P2 (A0H)
P3 (B0H)
P0 (80H)
P1 (90H)
PxM1.y
Tristate Ports Fuse = FFH (1)
0
1
0
1
Table 3-3 on page
Port Mode
Quasi-bidirectional
Push-pull Output
Input Only (High Impedance)
Open-Drain Output
Port Configuration
P0M0 (D4H), P0M1 (D5H)
P1M0 (E6H), P1M1 (E7H)
P2M0 (D6H), P2M1 (D7H)
P3M0 (DEH), P3M1 (CFH)
P4M0 (BEH), P4M1 (BFH)
C7
FF
FF
FF
FF
FF
00
00
00
03
19).
Tristate Ports Fuse = 00H (0)
FF
FF
00
00
00
00
00
00
03
03
3714A–MICRO–711