AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 51

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Figure 6-7.
3714A–MICRO–7/11
SIX2
T2X2
T1X2
T0X2
X2
Symbol
SYSTEM CLOCK
Function
UART Clock. In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two clock
periods per peripheral clock cycle (only valid when X2 = 1). In Fast Mode, clear for one system clock period and set for
TPS+1 clocks per peripheral clock cycle. This bit affects the generated baud rate during modes 0 and 2.
Timer 2 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle. This bit affects the timer increment/decrement rate.
Timer 1 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle. This bit affects the timer increment rate.
Timer 0 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle. This bit affects the timer increment rate.
CPU Clock. In Compatibility Mode, clear for 12 clock periods per machine cycle and set for 6 clock periods per machine
cycle. In Fast Mode, clear for two clock periods per instruction cycle and set for one clock periods per instruction cycle.
The default state of X2 is set by the X2 Fuse. See
Peripheral Clock Selection
÷(TPS+1)
÷2
Compatibility Mode
÷2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
AT89LP51RD2/ED2/ID2 Preliminary
Timer 0
Timer 1
Timer 2
Watchdog
PCA
(CPS = 00B)
PCA
(CPS = 01B)
UART
SPI
TWI
Section 24.2 on page
SYSTEM CLOCK
190.
÷(TPS+1)
Fast Mode
÷2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Timer 0
Timer 1
Timer 2
Watchdog
PCA
(CPS = 00B)
PCA
(CPS = 01B)
UART
SPI
TWI
51