ATmega1284 Atmel Corporation, ATmega1284 Datasheet - Page 313
ATmega1284
Manufacturer Part Number
ATmega1284
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1284
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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27.8.2
8272C–AVR–06/11
Serial Programming Algorithm
When writing serial data to the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P,
data is clocked on the rising edge of SCK.
When reading data from the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data
is clocked on the falling edge of SCK. See
To program and verify the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P in the
serial programming mode, the following sequence is recommended (See four byte instruction
formats in
1. Power-up sequence:
2. Wait for at least 20ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of synchro-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
5. The EEPROM array is programmed one byte at a time by supplying the address and data
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
time by supplying the 7 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the address
lines 15..8. Before issuing this command, make sure the instruction Load Extended
Address Byte has been used to define the MSB of the address. The extended address
byte is stored until the command is re-issued, i.e., the command needs only be issued for
the first page, and when crossing the 64KWord boundary. If polling (
used, the user must wait at least t
16.) Accessing the serial programming interface before the Flash write operation com-
pletes can result in incorrect programming.
together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
at least t
device, no 0xFFs in the data file(s) need to be programmed.
tent at the selected address at serial output MISO. When reading the Flash memory, use
the instruction Load Extended Address Byte to define the upper address byte, which is
not included in the Read Program Memory instruction. The extended address byte is
stored until the command is re-issued, i.e., the command needs only be issued for the
first page, and when crossing the 64KWord boundary.
operation.
Set RESET to “1”.
Turn V
Table
CC
WD_EEPROM
power off.
ATmega164A/PA/324A/PA/644A/PA/1284/P
27-17):
before issuing the next byte. (See
CC
and GND while RESET and SCK are set to “0”. In some sys-
WD_FLASH
Figure 27-12
before issuing the next page. (See
for timing details.
Table
27-16.) In a chip erased
RDY/BSY
) is not
Table 27-
313
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