ATmega1284P Atmel Corporation, ATmega1284P Datasheet - Page 65
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ATmega1284P
Manufacturer Part Number
ATmega1284P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1284P
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.2.1
12.3
12.3.1
8272C–AVR–06/11
Register Description
Moving Interrupts Between Application and Boot Space
MCUCR – MCU Control Register
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
Note:
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section
details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must
be followed to change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See the following Code Example.
Bit
0x35 (0x55)
Read/Write
Initial Value
...
0x1F036
;
0x1F03E RESET: ldi
0x1F03F
0x1F040
0x1F041
0x1F042
0x1FO43
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
1. Only available in the ATmega164PA/324PA/644PA/1284P.
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
for details on Boot Lock bits.
ATmega164A/PA/324A/PA/644A/PA/1284/P
JTD
R/W
7
0
...
jmp
out
ldi
out
sei
<instr>
BODS
R/W
6
0
(1)
...
SPM_RDY
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
BODSE
xxx
R/W
5
0
(1)
PUD
R/W
4
0
;
; SPM Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
”Memory Programming” on page 297
R
3
–
0
”Memory Programming” on page 297
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
0
0
MCUCR
for
65
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