ATmega324P Automotive Atmel Corporation, ATmega324P Automotive Datasheet - Page 20

• Manufacturer Part Number: ATmega324P Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega324P Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.3.1
20
ATmega164P/324P/644P
Data Memory Access Times
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the
1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible
through all these addressing modes. The Register File is described in
ter File” on page
Figure 6-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 6-3.
Address
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
12.
CPU
RD
Compute Address
(1024/2048/4096 x 8)
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
T1
Memory Access Instruction
Address valid
CPU
T2
cycles as described in
$10FF
$0000 - $001F
$0020 - $005F
$0060 - $00FF
$0100
Next Instruction
T3
“General Purpose Regis-
Figure
7674F–AVR–09/09
6-3.