ATmega329PA Atmel Corporation, ATmega329PA Datasheet - Page 62
ATmega329PA
Manufacturer Part Number
ATmega329PA
Description
Manufacturer
Atmel Corporation
Specifications of ATmega329PA
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
NXP
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12 000
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ATmega329PA-AU
Manufacturer:
AT
Quantity:
20 000
Part Number:
ATmega329PA-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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Company:
Part Number:
ATmega329PA-MUR
Manufacturer:
ATMEL
Quantity:
101
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13.2
13.3
13.3.1
8284D–AVR–6/11
Pin Change Interrupt Timing
Register Description
EICRA – External Interrupt Control Register A
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
An example of timing of a pin change interrupt is shown in
Figure 13-1. Pin Change Interrupt
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Bit
(0x69)
Read/Write
Initial Value
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
R
7
–
0
LE
Table 13-1 on page
pin_lat
R
6
–
0
D
Q
pin_sync
R
5
–
0
PCINT(0) in PCMSK(x)
R
4
–
0
63. The value on the INT0 pin is sampled before
pcint_in_(0)
0
x
R
clk
3
–
0
Figure
R
2
–
0
pcint_syn
13-1.
ISC01
R/W
1
0
pcint_setflag
ISC00
R/W
0
0
PCIF
EICRA
62
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