ATmega8535 Atmel Corporation, ATmega8535 Datasheet - Page 149

• Manufacturer Part Number: ATmega8535
• Manufacturer: Atmel Corporation

Specifications of ATmega8535

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock
Frame Formats
2502K–AVR–10/06
input (Slave) or clock output (Master). The dependency between the clock edges and
data sampling or data change is the same. The basic principle is that data input (on
RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is
changed.
Figure 71. Synchronous Mode XCK Timing
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and
which is used for data change. As Figure 71 shows, when UCPOL is zero the data will
be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the
data will be changed at falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start
and stop bits), and optionally a parity bit for error checking. The USART accepts all 30
combinations of the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next
data bits, up to a total of nine, are succeeding, ending with the most significant bit. If
enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-
plete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. Figure 72 illustrates the possible
combinations of the frame formats. Bits inside brackets are optional.
Figure 72. Frame Formats
St
(n)
P
UCPOL = 1
UCPOL = 0
1 start bit
5, 6, 7, 8, or 9 data bits
no even or odd parity bit
1 or 2 stop bits
(IDLE)
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
RxD / TxD
RxD / TxD
St
XCK
XCK
0
1
2
3
4
FRAME
[5]
[6]
[7]
[8]
ATmega8535(L)
[P]
Sample
Sample
Sp1 [Sp2]
(St / IDLE)
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