ATtiny2313A Atmel Corporation, ATtiny2313A Datasheet - Page 139

• Manufacturer Part Number: ATtiny2313A
• Manufacturer: Atmel Corporation

Specifications of ATtiny2313A

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.10.3
8246B–AVR–09/11
UCSRB – USART Control and Status Register B
• Bit 2 – UPE: USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer
(UDR) is read. Always set this bit to zero when writing to UCSRA.
• Bit 1 – U2X: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer rate for asynchronous communication.
• Bit 0 – MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address infor-
mation will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed
information see
• Bit 7 – RXCIE: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the RXC bit in UCSRA is set.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt
will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the TXC bit in UCSRA is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDRE bit in UCSRA is set.
• Bit 4 – RXEN: Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FE, DOR, and UPE Flags.
• Bit 3 – TXEN: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero)
will not become effective until ongoing and pending transmissions are completed, i.e., when the
Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted.
When disabled, the Transmitter will no longer override the TxD port.
Bit
0x0A (0x2A)
Read/Write
Initial Value
RXCIE
R/W
7
0
“Multi-processor Communication Mode” on page
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
UCSZ2
R/W
2
0
ATtiny2313A/4313
RXB8
136.
R
1
0
TXB8
R/W
0
0
UCSRB
139