ATtiny24 Atmel Corporation, ATtiny24 Datasheet - Page 112

• Manufacturer Part Number: ATtiny24
• Manufacturer: Atmel Corporation

Specifications of ATtiny24

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.11.4
12.11.5
12.11.6
112
ATtiny24/44/84
TCNT1H and TCNT1L – Timer/Counter1
OCR1AH and OCR1AL – Output Compare Register 1 A
OCR1BH and OCR1BL – Output Compare Register 1 B
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bits 5:0 – Res: Reserved Bits
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when the register is written.
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
Registers” on page
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See
Bit
0x2D (0x4D)
0x2C (0x4C)
Read/Write
Initial Value
Bit
0x2B (0x4B)
0x2A (0x4A)
Read/Write
Initial Value
Bit
0x29 (0x49)
0x28 (0x48)
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
“Accessing 16-bit Registers” on page
105.
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
OCR1A[15:8]
OCR1B[15:8]
TCNT1[15:8]
OCR1A[7:0]
OCR1B[7:0]
TCNT1[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
105.
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
“Accessing 16-bit
R/W
R/W
R/W
0
0
0
0
0
0
8006K–AVR–10/10
OCR1AH
OCR1AL
OCR1BH
OCR1BL
TCNT1H
TCNT1L