ATtiny24 Atmel Corporation, ATtiny24 Datasheet - Page 56

• Manufacturer Part Number: ATtiny24
• Manufacturer: Atmel Corporation

Specifications of ATtiny24

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

10.1.2
10.1.3
10.1.4
56
ATtiny24/44/84
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b10) as an intermediate step.
Table 10-1
Table 10-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
DDxn
0
0
0
1
1
PORTxn
summarizes the control signals for the pin value.
INSTRUCTIONS
0
1
1
0
1
Port Pin Configurations
SYSTEM CLK
SYNC LATCH
PINxn
(in MCUCR)
r17
PUD
X
X
X
0
1
Figure 10-2 on page
XXX
Output
Output
Input
Input
Input
I/O
t
pd, max
Pull-up
0x00
Yes
No
No
No
No
XXX
55, the PINxn Register bit and the preced-
t
pd, min
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
pd,max
in r17, PINx
and t
pd,min
0xFF
respectively.
8006K–AVR–10/10
Figure 10-3