ATtiny24 Atmel Corporation, ATtiny24 Datasheet - Page 155

• Manufacturer Part Number: ATtiny24
• Manufacturer: Atmel Corporation

Specifications of ATtiny24

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.5
18.6
18.6.1
18.6.2
8006K–AVR–10/10
EEPROM Write Prevents Writing to SPMCSR
Reading Lock, Fuse and Signature Data from Software
Reading Lock Bits from Firmware
Reading Fuse Bits from Firmware
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible for firmware to read device fuse and lock bits. In addition, firmware can also read
data from the device signature imprint table (see
Note:
Lock bit values are returned in the destination register after an LPM instruction has been issued
within three CPU cycles after RFLB and SELFPRGEN bits have been set in SPMCSR. The
RFLB and SELFPRGEN bits automatically clear upon completion of reading the lock bits, or if no
LPM instruction is executed within three CPU cycles, or if no SPM instruction is executed within
four CPU cycles. When RFLB and SELFPRGEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
If successful, the contents of the destination register are as follows.
See section
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,
only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:
If successful, the contents of the destination register are as follows.
Refer to
Bit
Rd
Bit
Rd
1. Load the Z-pointer with 0x0001.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the lock bits from the LPM destination register.
1. Load the Z-pointer with 0x0000.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the FLB from the LPM destination register.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-
grammed, will be read as one.
Table 19-5 on page 161
“Program And Data Memory Lock Bits” on page 159
FLB7
7
–
7
FLB6
6
–
6
for a detailed description and mapping of the Fuse Low Byte.
FLB5
5
–
5
FLB4
4
–
4
page
FLB3
3
–
3
161).
FLB2
2
–
2
for more information.
ATtiny24/44/84
FLB1
LB2
1
1
FLB0
LB1
0
0
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