ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 141
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ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 141 of 225
- Download datasheet (4Mb)
7701E–AVR–02/11
The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the
moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps
running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single-ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the ana-
log circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal con-
version and 14.5 ADC clock cycles after the start of a first conversion. When a conversion is
complete, the result is written to the ADC data registers, and ADIF is set. In single-conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When auto triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the sam-
ple-and-hold takes place two ADC clock cycles after the rising edge on the trigger source
signal. Three additional CPU clock cycles are used for synchronization logic.
In free running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see
page
Figure 18-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 18-5. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
142.
1
1
2
MUX and REFS
Update
2
MUX and REFS
Update
12
Atmel ATtiny24/44/84 [Preliminary]
3
13
Sample & Hold
4
14
5
15
6
Sample & Hold
16
First Conversion
17
7
One Conversion
18
8
19
9
20
10
Conversion
Complete
21
11
22
Conversion
Complete
23
12
24
13
25
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
Next Conversion
1
Next
Conversion
1
LSB of Result
Table 18-1 on
2
2
MUX and REFS
Update
MUX and REFS
Update
3
3
141
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