ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 25
ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
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- ATTINY25_AUTOMOTIVE PDF datasheet #3
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7. System Clock and Clock Options
7.1
7.1.1
7.1.2
7.1.3
7701E–AVR–02/11
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
I/O
CPU
Figure 7-1 on page 25
All of the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as described
in
Figure 7-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from perform-
ing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like the Timer/Counter. The I/O clock
is also used by the External Interrupt module, but note that some external interrupts are
detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is
halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active
simultaneously with the CPU clock.
FLASH
“Power Management and Sleep Modes” on page
Clock Distribution
ADC
External Clock
clk
clk
ADC
I/O
Source clock
presents the principal clock systems in the AVR
General I/O
Atmel ATtiny24/44/84 [Preliminary]
System Clock
Modules
Control Unit
AVR Clock
Multiplexer
Prescaler
Clock
Calibrated RC
Oscillator
Oscillator
Crystal
Reset Logic
CPU Core
clk
clk
CPU
FLASH
Crystal Oscillator
Low-Frequency
Watchdog Timer
Watchdog clock
34. The clock systems are detailed below.
RAM
Watchdog
Oscillator
Flash and
EEPROM
®
Calibrated RC
and their distribution.
Oscillator
25
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