ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 16
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ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 16 of 225
- Download datasheet (4Mb)
6.2.1
16
Atmel ATtiny24/44/84 [Preliminary]
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and 128/256/512 bytes of internal
data SRAM in the Atmel
modes. The Register File is described in
Figure 6-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
page
Figure 6-3.
16.
Address
Data Memory Map
On-chip Data SRAM Access Cycles
clk
Data
Data
WR
CPU
RD
®
(128/256/512 x 8)
64 I/O Registers
Data Memory
ATtiny24/44/84 are all accessible through all these addressing
Internal SRAM
Compute Address
32 Registers
T1
Memory Access Instruction
“General Purpose Register File” on page
0x0DF/0x015F/0x025F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Address valid
T2
CPU
cycles as described in
Next Instruction
T3
Figure 6-3 on
7701E–AVR–02/11
10.
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