ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 100
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ATUC64D3
Manufacturer Part Number
ATUC64D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
9.2.13
9.2.13.1
9.2.14
9.2.14.1
9.2.14.2
32002F–03/2010
Messages
Registers
Debug Status (DEBS)
Device ID Register (DID)
Nexus Configuration Register (NXCFG)
When an interrupt occurd the CPU will jump to the interrupt handler routine and process the
interrupt. The interrupt handler must clear the interrupt before leaving this routing. This is done
by witing a zero to DCEMUDI or DCCPURI for DCEMU reads and DCCPU writes respectively:
This message is output when the CPU enters or exits Debug Mode or a low-power mode. The
message is output whenever the AUX port is enabled. The STATUS field of this message con-
tains the information in the Development Status register. The field will contain these values:
Table 9-4.
The Device ID Register (DID) provides key attributes to the development tool concerning the
embedded processor. This is the same as the value returned by the JTAG ID instruction.
Table 9-5.
The Nexus Configuration Register (NXCFG) provides key information about the specific imple-
mentation of the CPU and OCD architecture, and the configuration of the Nexus development
Debug Status Message
Packet
Size
32
6
R/W
R
R
R
R
• Turn off the interrupt masks in the CPU
• The CPU enters Debug Mode: STATUS bits indicate cause of entry to Debug Mode. DBS is
• The CPU exits Debug Mode: STATUS = 0. This includes exiting Debug Mode by writing
• The CPU enters a low-power mode: Only the STP bit is set, while the other bits are zero.
• The CPU exits a low-power mode: STATUS = 0
set if OCD Mode was entered.
DC:RES.
Bit Number
31:28
27:12
11:1
0
Packet
Name
STATUS
TCODE
Debug Status
DID Register
Field Name
RN
PN
MID
Reserved
Packet
Type
Fixed
Fixed
Description
The contents of the Development Status register.
Value = 0
Init. Val.
Part
specific
Part
specific
0x01F
1
Description
RN - Revision Number
PN - Product Number
Manufacturer ID
0x01F = ATMEL
Reserved
This bit always reads as 1
AVR32
100