ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 21
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ATUC64D3
Manufacturer Part Number
ATUC64D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
3.4
3.4.1
3.4.2
3.4.3
32002F–03/2010
EX pipeline stage
ALU section
Multiply section
Load-store section
The Execute (EX) pipeline stage performs register file reads, operations on registers and mem-
ory, and register file writes.
The ALU pipeline performs most of the data manipulation instructions, like arithmetical and logi-
cal operations. The ALU stage performs the following tasks:
All multiply instructions execute in the multiply section. This section implements a 32 by 32 mul-
tiplier array, and 16x16, 32x16 and 32x32 multiplications and multiply-accumulates therefore
have an issue latency of one cycle. Multiplication of 32 by 32 bits to a 64-bit result require two
iterations through the multiplier array, and therefore needs several cycles to complete. This will
stall the multiply pipeline until the instruction is complete.
A special accumulator cache is implemented in the MUL section. This cache saves the multiply-
accumulate result in dedicated registers in the MUL section, as well as writing them back to the
register file. This allows subsequent MAC instructions to read the accumulator value from the
cache, instead of from the register file. This will speed up MAC operations by one clock cycle. If
a MAC instruction targets a register not found in the cache, one clock cycle is added to the MAC
operation, loading the accumulator value from the register file into the cache. In the next cycle,
the MAC operation is restarted automatically by hardware. If an instruction, like an add, mul or
load, is executed with target address equal to that of a valid cached register, the instruction will
update the cache.
The accumulator cache can hold one doubleword accumulator value, or one word accumulator
value. Hardware ensures that the accumulator cache is kept consistent. If another pipeline sec-
tion writes to one of the registers kept in the accumulator cache, the cache is updated. The
cache is automatically invalidated after reset.
The load-store (LS) pipeline is able to read or write one register per clock cycle. The address is
calculated by the ALU section. Thereafter the address is passed on to the LS section and output
to the memory interface, together with the data to write if the access is a write. If the access is a
read, the read data is returned from the memory interface in the same cycle. If the read data
requires typecasting or other manipulation like performed by ldins or ldswp, this manipulation is
performed in the same cycle.
Any load or store multiple registers are decoded by the ID stage and passed on to the EX stage
as a series of single load or store word operations.
• Target address calculation and condition check for change-of-flow instructions.
• Condition code checking for conditional instructions.
• Address calculation for memory accesses
• Writeback address calculation for the LS pipeline.
• All flag setting for arithmetical and logical instructions.
• The saturation needed by satadd and satsub.
• The operation needed by satrnds, satrndu, sats and satu.
• Signed and unsigned division
AVR32
21