ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 136
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ATUC64D3
Manufacturer Part Number
ATUC64D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
9.6.4
9.6.4.1
9.6.4.2
9.7
9.7.1
32002F–03/2010
Ownership Trace
Registers
Functional description
Data Trace Control register (DTC)
Data Trace Start/End Address register (DTSA/DTEA)
This register controls actions taken on data accesses within all data trace channels.
Table 9-49.
DTSAn and DTEAn define the inclusive data access range [DTSAn : DTEAn] for trace channel
n. Each trace channel 0 and 1 has its own DTSA/DTEA register pair. If DTSA=DTEA, the trace
channel will match on accesses to a single location. If DTSA>DTEA, no match will occur for the
trace channel.
DTSA0, DTSA1
Table 9-50.
DTEA0, DTEA1
Table 9-51.
The AVR32 OCD system implements Ownership Trace in compliance with the Nexus standard.
Ownership trace provides a macroscopic view, such as task flow reconstruction, when debug-
ging software written in a high level (or object oriented) language. It offers the highest level of
abstraction for tracking operating system software execution. This is especially useful when the
developer is not interested in debugging at lower levels.
Ownership trace is especially important for embedded processors with a memory management
unit, in which all processes can use the same virtual program and data spaces. Ownership trace
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit Number
31:30
29:28
27:2
1
0
Data Trace Control Register
Data Trace Start Address Register
Data Trace End Address Register
Bit Number
31:0
Bit Number
31:0
Field Name
RWT0
RWT1
Reserved
T1WP
T0WP
Field Name
DTSA
Field Name
DTEA
Init. Val.
0
0
0
0
0
Init. Val.
0
Init. Val.
0
Description
RWT0 - Read/Write Trace channel 0
00 = No trace enabled
x1 = Enable data read trace
1x = Enable data write trace
RWT1 - Read/Write Trace channel 1
00 = No trace enabled
x1 = Enable data read trace
1x = Enable data write trace
T1WP - Trace Channel 1 Watchpoint
T0WP - Trace Channel 0 Watchpoint
Description
DTSA - Start address for trace visibility
Description
DTEA - End address for trace visibility
AVR32
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