ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 238

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3
8291A–AVR–10/11
General TWI Bus Concepts
The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial
clock line (SCL) and a serial data line (SDA). The two lines are open-collector lines (wired-AND),
and pull-up resistors (Rp) are the only external components needed to drive the bus. The pull-up
resistors provide a high level on the lines when none of the connected devices are driving the
bus
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus.
A device connected to the bus can be a master or slave, where the master controls the bus and
all communication.
Figure 19-1 on page 238
Figure 19-1. TWI bus topology.
A unique address is assigned to all slave devices connected to the bus, and the master will use
this to address a slave and initiate a data transaction.
Several masters can be connected to the same bus, called a multi-master environment. An arbi-
tration mechanism is provided for resolving bus ownership among masters, since only one
master device may own the bus at any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by
responding to more than one address.
A master indicates the start of a transaction by issuing a START condition (S) on the bus. An
address packet with a slave address (ADDRESS) and an indication whether the master wishes
to read or write data (R/W) are then sent. After all data packets (DATA) are transferred, the mas-
ter issues a STOP condition (P) on the bus to end the transaction. The receiver must
acknowledge (A) or not-acknowledge (A) each byte received.
Figure 19-2 on page 239
SDA
SCL
V
CC
R
P
R
P
illustrates the TWI bus topology.
shows a TWI transaction.
DEVICE #1
TWI
R
S
R
S
DEVICE #2
TWI
R
Atmel AVR XMEGA B
S
R
S
Note: R
DEVICE #N
TWI
R
S
S
is optional
R
S
238