ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 248

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.6.1.3
19.6.1.4
19.6.2
19.6.3
19.7
8291A–AVR–10/11
Enabling External Driver Interface
Receiving Data Packets
Transmitting Data Packets
Case S3: Collision
Case S4: STOP condition received.
received. Data, repeated START, or STOP can be received after this. If NACK is sent, the slave
will wait for a new START condition and address match.
If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the
data and acknowledge output from the slave logic. The clock hold is released. A START or
repeated START condition will be accepted.
When the STOP condition is received, the slave address/stop flag will be set, indicating that a
STOP condition, and not an address match, occurred.
The slave will know when an address packet with R/W direction bit cleared has been success-
fully received. After acknowledging this, the slave must be ready to receive data. When a data
packet is received, the data interrupt flag is set and the slave must indicate ACK or NACK. After
indicating a NACK, the slave must expect a STOP or repeated START condition.
The slave will know when an address packet with R/W direction bit set has been successfully
received. It can then start sending data by writing to the slave data register. When a data packet
transmission is completed, the data interrupt flag is set. If the master indicates NACK, the slave
must stop transmitting data and expect a STOP or repeated START condition.
An external driver interface can be enabled. When this is done, the internal TWI drivers with
input filtering and slew rate control are bypassed. The normal I/O pin function is used, and the
direction must be configured by the user software. When this mode is enabled, an external TWI
compliant tri-state driver is needed for connecting to a TWI bus.
By default, port pins 0 (Pn0) and 1 (Pn1) are used for SDA and SCL. The external driver inter-
face uses port pins 0 to 3 for the SDA_IN, SCL_IN, SDA_OUT, and SCL_OUT signals.
Atmel AVR XMEGA B
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