ATxmega192A3 Atmel Corporation, ATxmega192A3 Datasheet - Page 27

• Manufacturer Part Number: ATxmega192A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega192A3

• Flash (kbytes): 192 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.15.8
4.15.9
8077H–AVR–12/09
CTRLA - Non-Volatile Memory Control Register A
CTRLB - Non-Volatile Memory Control Register B
• Bit 7:1 - Reserved Bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - CMDEX: Non-Volatile Memory Command Execute
Setting this bit will execute the command in the CMD register. This bit is protected by the Config-
uration Change Protection (CCP) mechanism, refer to
Protection” on page 12
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3 - EEMAPEN: EEPROM Data Memory Mapping Enable
Setting this bit will enable Data Memory Mapping of the EEPROM section. The EEPROM can
then be accessed using Load and Store instructions.
• Bit 2 - FPRM: Flash Power Reduction Mode
Setting this bit will enable power saving for the flash memory. The section not being accessed
will be turned off like in sleep mode. If code is running from Application Section, the Boot Loader
Section will be turned off and vice versa. If access to the section that is turned off is required, the
CPU will be halted equally long to the start-up time from the Idle sleep mode.
• Bit 1 - EPRM: EEPROM Power Reduction Mode
Setting this bit will enable power saving for the EEPROM memory. The EEPROM will then be
powered down equal to entering sleep mode. If access is required, the bus master will be halted
equally long as the start-up time from Idle sleep mode.
• Bit 0 - SPMLOCK: SPM Locked
The SPM Locked bit can be written to prevent all further self-programming. The bit is cleared at
reset and cannot be cleared from software. This bit is protected by the Configuration Change
Protection (CCP) mechanism, refer to
12
Bit
+0x0B
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
for details on the CCP.
R
7
0
-
R
7
0
-
R
6
0
for details on the CCP.
-
R
6
0
-
R
5
0
-
R
5
0
-
R
4
0
-
Section 3.12 ”Configuration Change Protection” on page
EEMAPEN
R
4
0
-
R/W
3
0
R
3
0
-
FPRM
R/W
2
0
Section 3.12 ”Configuration Change
R
2
0
-
EPRM
R/W
1
0
R
1
0
-
SPMLOCK
XMEGA A
R/W
CMDEX
0
0
S
0
0
CTRLA
CTRLB
27