ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 22
ATxmega64A3U
Manufacturer Part Number
ATxmega64A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A3U
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A3U-AU
Manufacturer:
ACTEL
Quantity:
101
Part Number:
ATxmega64A3U-MH
Manufacturer:
TI/德州仪器
Quantity:
20 000
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4.5
4.6
8331A–AVR–07/11
Data Memory
Internal SRAM
The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or
write access should be blocked). Lock bits can be written by external programmers and applica-
tion software, but only to stricter protection levels. Chip erase is the only way to erase the lock
bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased
after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit
will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
The data memory contains the I/O memory, internal SRAM, optionally memory mapped
EEPROM, and external memory, if available. The data memory is organized as one continuous
memory section, as shown in
Figure 4-2.
I/O memory, EEPROM, and SRAM will always have the same start addresses for all XMEGA
devices. The address space for external memory will always start at the end of internal SRAM
and end at address 0xFFFFFF.
The internal SRAM always starts at hexadecimal address 0x2000. SRAM is accessed by the
CPU using the load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
Data memory map.
Figure 4-2 on page
22.
Atmel AVR XMEGA AU
22
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