ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 345

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.10.3
27.10.4
8331A–AVR–07/11
REFRESH – SDRAM Refresh Period Register
INITDLY – SDRAM Initialization Delay Register
Table 27-14. SDRAM Column Bits
• Bit 15:10 – Reserved
These bits are reserved and will always be read as zero.
• Bit 9:0 – REFRESH[9:0]: SDRAM Refresh Period
This register sets the refresh period as a number of Clk
another external memory access at time of refresh, up to 4 refresh will be remembered and
given at the first available time.
• Bit 15:14 – Reserved
These bits are reserved and will always be read as zero.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x07
Read/Write
Initial Value
SDCOL[1:0]
00
01
10
11
R/W
R/W
R
R
7
0
7
–
0
7
0
7
–
0
R/W
R/W
R
R
6
0
6
–
0
6
0
6
–
0
Group Configuration
8BIT
9BIT
10BIT
11BIT
R/W
R/W
R/W
5
0
5
–
R
0
5
0
5
0
R/W
R/W
R/W
4
0
4
–
R
0
4
0
4
0
REFRESH[7:0]
INITDLY[7:0]
Description
8 Column Bits
9 Column Bits
10 Column Bits
11 Column Bits
R/W
R/W
R/W
3
0
3
–
R
0
3
0
3
0
Atmel AVR XMEGA AU
INITDLY[13-8]
PER2
R/W
R/W
R/W
2
0
2
–
R
0
2
0
2
0
cycles. If the EBI is busy with
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
REFRESH[9-8]
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
REFRESHL
REFRESHH
INITDLYH
INTDLYL
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