M40800 Atmel Corporation, M40800 Datasheet - Page 15

• Manufacturer Part Number: M40800
• Manufacturer: Atmel Corporation

Specifications of M40800

• Flash (kbytes): 0 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 40 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: No

ARM DDI 0029G
Figure 7-23
Figure B-1
Figure B-2
Figure B-3
Figure B-4
Figure B-5
Figure B-6
Figure B-7
Figure B-8
Figure B-9
Figure B-10
Figure B-11
APE control timing ................................................................................................... 7-27
ARM7TDMI core scan chain arrangements .............................................................. B-4
Test access port controller state transitions .............................................................. B-5
ID code register format ............................................................................................ B-14
Input scan cell ......................................................................................................... B-17
Clock switching on entry to debug state .................................................................. B-22
Debug exit sequence .............................................................................................. B-28
EmbeddedICE block diagram ................................................................................. B-41
Watchpoint control value and mask format ............................................................. B-42
Debug control register format .................................................................................. B-48
Debug status register format ................................................................................... B-50
Debug control and status register structure ............................................................ B-51
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