RM9200 Atmel Corporation, RM9200 Datasheet - Page 114
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RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- RM9200 PDF datasheet #3
- RM9200 PDF datasheet #4
- RM9200 PDF datasheet #5
- RM9200 PDF datasheet #6
- Current page: 114 of 284
- Download datasheet (2Mb)
Coprocessor Interface
4.4.6
4.4.7
4-10
Execute stage
Decode stage
coprocessor)
coprocessor)
Fetch stage
(from ARM)
Coprocessor data operations
Coprocessor load and store operations
CPA (from
CPB (from
D[31:0]
MCLK
nCPI
Coprocessor data operations, CDP instructions, perform processing operations on the
data held in the coprocessor register bank. No information is transferred between the
ARM7TDMI processor and the coprocessor as a result of this operation. An example
sequence is shown in Figure 4-3.
The coprocessor load and store instructions are used to transfer data between a
coprocessor and memory. They can be used to transfer either a single word of data, or
a number of the coprocessor registers. There is no limit to the number of words of data
that can be transferred by a single LDC or STC instruction, but by convention no more
than 16 words should be transferred in a single instruction. An example sequence is
shown in Figure 4-4 on page 4-11.
If you transfer more than 16 words of data in a single instruction, the worst case
interrupt latency of the ARM7TDMI processor increases.
ADD
Instr fetch
(ADD)
Note
Copyright © 1994-2001. All rights reserved.
ADD
SUB
Instr fetch
(SUB)
MCR
SUB
ADD
Instr fetch
(MCR)
Figure 4-3 Coprocessor data operation sequence
MCR
SUB
TST
Instr fetch
(TST)
MCR
SUB
TST
Instr fetch
(SUB)
SUB
TST
Instr fetch
ARM DDI 0029G
SUB
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