RM9200 Atmel Corporation, RM9200 Datasheet - Page 67

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.8.7
2.8.8
2.8.9
ARM DDI 0029G
Software interrupt instruction
Undefined instruction
Exception vectors
Address
The Software Interrupt instruction (SWI) is used to enter Supervisor mode, usually to
request a particular supervisor function. The SWI handler reads the opcode to extract
the SWI function number.
A SWI handler returns by executing the following irrespective of the processor
operating state:
This action restores the PC and CPSR, and returns to the instruction following the SWI.
When the ARM7TDMI processor encounters an instruction that neither it, nor any
coprocessor in the system can handle, the ARM7TDMI core takes the undefined
instruction trap. Software can use this mechanism to extend the ARM instruction set by
emulating undefined coprocessor instructions.
After emulating the failed instruction, the trap handler executes the following
irrespective of the processor operating state:
This action restores the CPSR and returns to the next instruction after the undefined
instruction.
For more information about undefined instructions, see the ARM Architecture Reference
Manual.
Table 2-4 lists the exception vector addresses. In this table, I and F represent the
previous value of the IRQ and FIQ interrupt disable bits respectively in the CPSR.
Exception
Reset
Undefined instruction
Software interrupt
Prefetch Abort
Copyright © 1994-2001. All rights reserved.
Mode on entry
Supervisor
Undefined
Supervisor
Abort
I state on entry
Set
Set
Set
Set
Table 2-4 Exception vectors
Programmer’s Model
F state on entry
Set
Unchanged
Unchanged
Unchanged
2-21