SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 266
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SAM7L128
Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L128
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B.15
B-48
The debug control register
The debug control register is 3 bits wide. Writing control bits occurs during a register
write access with the read/write bit HIGH. Reading control bits occurs during a register
read access with the read/write bit LOW.
Figure B-9 on page B-48 shows the function of each bit in this register.
If Bit 2, INTDIS, is asserted, the interrupt enable signal, IFEN of the core is forced
LOW. Therefore. all interrupts, IRQ and FIQ, are disabled during debugging,
DBGACK is HIGH, or if the INTDIS bit is asserted. The IFEN signal is driven as listed
in Table B-7 on page B-48.
Bits 1 and 0 enable the values on DBGRQ and DBGACK to be forced.
Figure B-11 on page B-51 shows that the value stored in bit 1 of the control register is
synchronized and then ORed with the external DBGRQ before being applied to the
processor. The output of this OR gate is the signal DBGRQI which is brought out
externally from the macrocell.
The synchronization between control bit 1 and DBGRQI is to assist in multiprocessor
environments. The synchronization latch only opens when the TAP controller state
machine is in the RUN-TEST-IDLE state. This enables an enter debug condition to be
set up in all the processors in the system while they are still running. When the condition
is set up in all the processors, it can then be applied to them simultaneously by entering
the RUN-TEST-IDLE state.
Copyright © 1994-2001. All rights reserved.
DBGACK
LOW
HIGH
x
Figure B-9 Debug control register format
INTDIS
2
Table B-7 Interrupt signal control
INTDIS
LOW
x
HIGH
DBGRQ
1
IFEN
HIGH
LOW
LOW
ARM DDI 0029G
DBGACK
Interrupts
Permitted
Inhibited
Inhibited
0
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