SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 91

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
The macrocell has an additional bus control signal, nENIN that allows the external
system to manually tristate the bus. In the simplest systems, nENIN can be tied LOW
and nENOUT can be ignored. In many applications, when the external data bus is a
shared resource, greater control might be required. In this situation, nENIN can be used
to delay when the external bus is driven.
For backwards compatibility, DBE is also included. At the macrocell level, DBE and
nENIN have almost identical functionality and in most applications one can be tied to
keep the data bus enabled.
The processor has another output control signal called TBE. This signal is usually only
used during test and must be tied HIGH when not in use. When driven LOW, TBE
forces all tristateable outputs to high impedance, it is as though both DBE and ABE
have been driven LOW, causing the data bus, the address bus, and all other signals
normally controlled by ABE to become high impedance.
There is no scan cell on TBE. Therefore, TBE is completely independent of scan data
and can be used to put the outputs into a high impedance state while scan testing takes
place.
Table 3-6 lists the tristate control of the processor outputs.
Note
Note
Copyright © 1994-2001. All rights reserved.
Table 3-6 Tristate control of processor outputs
Processor output
A[31:0]
D[31:0]
nRW
LOCK
MAS[1:0]
nOPC
nTRANS
ABE
Yes
-
Yes
Yes
Yes
Yes
Yes
Memory Interface
DBE
-
Yes
-
-
-
-
-
TBE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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