SAM7L64 Atmel Corporation, SAM7L64 Datasheet - Page 112

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SAM7L64

Manufacturer Part Number
SAM7L64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7L64

Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Coprocessor Interface
4.4.4
4-8
Decode stage
Fetch stage
Execute
D[31:0]
Consequences of busy-waiting
MCLK
stage
nCPI
CPA
CPB
ADD
Instr fetch
(ADD)
CPA and CPB are ignored by the ARM7TDMI processor when it does not have a
undefined or coprocessor instruction in the Execute stage of the pipeline.
A summary of coprocessor signaling is listed in Table 4-3 on page 4-7.
A busy-waited coprocessor instruction can be interrupted. If a valid FIQ or IRQ occurs
and the appropriate bit is clear in the CSPR, then the ARM7TDMI processor abandons
the coprocessor instruction, and signals this by taking nCPI HIGH. A coprocessor that
is capable of busy-waiting must monitor nCPI to detect this condition. When the
ARM7TDMI core abandons a coprocessor instruction, the coprocessor also abandons
the instruction, and continues tracking the ARM7TDMI processor pipeline.
ADD
SUB
Instr fetch
(SUB)
Copyright © 1994-2001. All rights reserved.
CDP
SUB
ADD
Instr fetch
(CDP)
CDP
TST
SUB
Instr fetch
(TST)
Instr fetch
(SUB)
Coprocessor
busy waiting
Figure 4-1 Coprocessor busy-wait sequence
CDP
SUB
TST
SUB
TST
Instr fetch
ARM DDI 0029G
SUB
Instr fetch

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