SAM7L64 Atmel Corporation, SAM7L64 Datasheet - Page 128
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SAM7L64
Manufacturer Part Number
SAM7L64
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L64
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug Interface
5.3
5.3.1
5-6
Debug interface signals
Entry into debug state
There are three primary external signals associated with the debug interface:
•
•
The following sections describe:
•
•
The ARM7TDMI processor is forced into debug state following a breakpoint,
watchpoint, or debug request.
You can use the EmbeddedICE Logic to program the conditions under which a
breakpoint or watchpoint can occur. Alternatively, you can use the BREAKPT signal
to allow external logic to flag breakpoints or watchpoints and monitor the following:
•
•
•
The timing is the same for externally-generated breakpoints and watchpoints. Data must
always be valid on the falling edge of MCLK. When this is an instruction to be
breakpointed, the BREAKPT signal must be HIGH on the next rising edge of MCLK.
Similarly, when the data is for a load or store, asserting BREAKPT on the rising edge
of MCLK marks the data as watchpointed.
When the processor enters debug state, the DBGACK signal is asserted. The timing for
an externally-generated breakpoint is shown in Figure 5-3 on page 5-7.
The following sections describe:
•
•
•
BREAKPT and DBGRQ are system requests for the processor to enter debug
state
DBGACK is used to indicate that the core is in debug state.
DBGEN must be configured HIGH to fully enable the debug features of the
processor. Refer to Disabling EmbeddedICE on page 5-15.
Entry into debug state on page 5-6
Action of the processor in debug state on page 5-9.
address bus
data bus
control signals.
Entry into debug state on breakpoint on page 5-7
Entry into debug state on watchpoint on page 5-8
Entry into debug state on debug request on page 5-8.
Copyright © 1994-2001. All rights reserved.
Note
ARM DDI 0029G
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