SAM7L64 Atmel Corporation, SAM7L64 Datasheet - Page 213
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SAM7L64
Manufacturer Part Number
SAM7L64
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L64
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
Name
IR[3:0]
TAP controller instruction register
ISYNC
Synchronous interrupts
LOCK
Locked operation
MAS[1:0]
Memory access size
MCLK
Memory clock input
nCPI
Not coprocessor instruction
nENIN
NOT enable input
Copyright © 1994-2001. All rights reserved.
Type
O4
IC
O8
O8
IC
O4
IC
Description
Reflects the current instruction loaded into the TAP controller instruction
register. These bits change on the falling edge of TCK when the state
machine is in the UPDATE-IR state.
The instruction encoding is described in Public instructions on page B-9.
Set this HIGH if nIRQ and nFIQ are synchronous to the processor
clock; LOW for asynchronous interrupts.
When the processor is performing a locked memory access this is HIGH.
This is used to prevent the memory controller allowing another device to
access the memory.
It is active only during the data swap (SWP) instruction.
This is one of the signals controlled by APE, ALE and ABE.
Used to indicate to the memory system the size of data transfer (byte,
halfword or word) required for both read and write cycles, become valid
before the falling edge of MCLK and remain valid until the rising edge
of MCLK during the memory cycle.
The binary values 00, 01, and 10 represent byte, halfword and word
respectively (11 is reserved).
This is one of the signals controlled by APE, ALE, and ABE.
This is the main clock for all memory accesses and processor operations.
The clock speed can be reduced to allow access to slow peripherals or
memory.
Alternatively, the nWAIT can be used with a free-running MCLK to
achieve the same effect.
LOW when a coprocessor instruction is processed. The processor then
waits for a response from the coprocessor on the CPA and CPB lines.
If CPA is HIGH when MCLK rises after a request has been initiated by
the processor, then the coprocessor handshake is aborted, and the
processor enters the undefined instruction trap.
If CPA is LOW at this time, then the processor will enters a busy-wait
period until CPB goes LOW before completing the coprocessor
handshake.
This must be LOW for the data bus to be driven during write cycles.
Can be used in conjunction with nENOUT to control the data bus during
write cycles.
See Chapter 3 Memory Interface.
Table A-3 Signal Descriptions (continued)
Signal Description
A-7
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