SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 124
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SAM7S16
Manufacturer Part Number
SAM7S16
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S16
Flash (kbytes)
16 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug Interface
5.1
5.1.1
5.1.2
5-2
About the debug interface
Stages of debug
Clocks
The ARM7TDMI processor debug interface is based on IEEE Std. 1149.1 - 1990,
Standard Test Access Port and Boundary-Scan Architecture. Refer to this standard for
an explanation of the terms used in this chapter and for a description of the Test Access
Port (TAP) controller states. A flow diagram of the TAP controller state transitions is
provided in Figure B-2 on page B-5.
The ARM7TDMI processor contains hardware extensions for advanced debugging
features. These make it easier to develop application software, operating systems and
the hardware itself.
The debug extensions enable you to force the core into debug state. In debug state, the
core is stopped and isolated from the rest of the system. This allows the internal state of
the core and the external state of the system, to be examined while all other system
activity continues as normal. When debug has completed, the debug host restores the
core and system state, program execution resumes.
A request on one of the external debug interface signals, or on an internal functional unit
known as the EmbeddedICE Logic, forces the ARM7TDMI processor into debug state.
The events that activate debug are:
•
•
•
The internal state of the ARM7TDMI processor is then examined using a JTAG-style
serial interface. This allows instructions to be inserted serially into the core pipeline
without using the external data bus. So, for example, when in debug state, a Store
Multiple (STM) can be inserted into the instruction pipeline and this exports the
contents of the ARM7TDMI core registers. This data can be serially shifted out without
affecting the rest of the system.
The ARM7TDMI core has two clocks:
•
•
During normal operation, the core is clocked by MCLK and internal logic holds DCLK
LOW.
a breakpoint, an instruction fetch
a watchpoint, a data access
an external debug request.
MCLK is the memory clock
DCLK is an internal debug clock, generated by the test clock, TCK.
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G
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