SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 62
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SAM7S16
Manufacturer Part Number
SAM7S16
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S16
Flash (kbytes)
16 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Programmer’s Model
2.8
2.8.1
2-16
Exception
or entry
BL
SWI
UDEF
PABT
Exceptions
Exception entry and exit summary
Return instruction
Exceptions arise whenever the normal flow of a program has to be halted temporarily,
for example, to service an interrupt from a peripheral. Before attempting to handle an
exception, the ARM7TDMI processor preserves the current processor state so that the
original program can resume when the handler routine has finished.
If two or more exceptions arise simultaneously, the exceptions are dealt with in the fixed
order given in Table 2-3.
This section provides details of the ARM7TDMI processor exception handling:
•
•
•
•
•
•
•
•
•
Table 2-3 summarizes the PC value preserved in the relevant r14 on exception entry, and
the recommended instruction for exiting the exception handler.
Exception entry and exit summary on page 2-16
Entering an exception on page 2-17
Leaving an exception on page 2-18
Fast interrupt request on page 2-18
Interrupt request on page 2-19
Software interrupt instruction on page 2-21
Undefined instruction on page 2-21
Exception vectors on page 2-21
Exception priorities on page 2-22.
Copyright © 1994-2001. All rights reserved.
Previous state ARM r14_x
Thumb r14_x
PC+4
PC+4
PC+4
PC+4
PC+2
PC+2
PC+2
PC+4
Remarks
Where PC is the address of the BL, SWI, or
undefined instruction fetch that had the
Prefetch Abort
Table 2-3 Exception entry and exit
ARM DDI 0029G
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