SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 83
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SAM7S16
Manufacturer Part Number
SAM7S16
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S16
Flash (kbytes)
16 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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3.4.5
3.4.6
3.4.7
ARM DDI 0029G
nTRANS
LOCK
TBIT
The nTRANS output conveys information about the transfer. A MMU can use this
signal to determine whether an access is from a privileged mode or User mode. This
signal can be used with nOPC to implement an access permission scheme. The
meaning of nTRANS is listed in Table 3-5.
More information relevant to the nTRANS signal and security is provided in Privileged
mode access on page 3-32.
LOCK is used to indicate to an arbiter that an atomic operation is being performed on
the bus. LOCK is normally LOW, but is set HIGH to indicate that a SWP or SWPB
instruction is being performed. These instructions perform an atomic read/write
operation, and can be used to implement semaphores.
TBIT is used to indicate the operating state of the ARM7TDMI processor. When in:
•
•
Memory systems do not usually have to use TBIT because MAS[1:0] indicates the size
of the instruction required.
ARM state, the TBIT signal is LOW
Thumb state, the TBIT signal is HIGH.
Note
Copyright © 1994-2001. All rights reserved.
nTRANS
0
1
Table 3-5 nTRANS encoding
Mode
User
Privileged
Memory Interface
3-13
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