SAM7X512 Atmel Corporation, SAM7X512 Datasheet - Page 261

• Manufacturer Part Number: SAM7X512
• Manufacturer: Atmel Corporation

Specifications of SAM7X512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
The bits have the following functions:
nRW
MAS[1:0]
The encoding is listed in Table B-6 on page B-43.
nOPC
nTRANS
EXTERN[1:0]
CHAIN
RANGE
Copyright © 1994-2001. All rights reserved.
Compares against the write signal from the core to detect the
direction of bus activity. nRW is 0 for a read cycle and 1 for a
write cycle.
Compares against the MAS[1:0] signal from the core to detect the
size of bus activity.
Detects if the current cycle is an instruction fetch, with nOPC=0,
or a data access, with nOPC=1.
Compares against the not translate signal from the core to
distinguish between User Mode, with nTRANS=0, and non-user
mode, with nTRANS=1, accesses.
Is an external input to EmbeddedICE that enables the watchpoint
to be dependent upon some external condition. The EXTERN
input for Watchpoint 0 is labeled EXTERN[0]. The EXTERN
input for Watchpoint 1 is labeled EXTERN[1].
Can be connected to the chain output of another watchpoint to
implement, for example, debugger requests of the form:
ARM7TDMI core EmbeddedICE Logic, the CHAINOUT output
of Watchpoint 1 is connected to the CHAIN input of Watchpoint
0. The CHAINOUT output is derived from a register. The
address/control field comparator drives the write enable for the
register. The input to the register is the value of the data field
comparator. The CHAINOUT register is cleared when the control
value register is written, or when nTRST is LOW.
Can be connected to another watchpoint unit.
bit 1
0
0
1
1
Table B-6 MAS[1:0] signal encoding
bit 0
0
1
0
1
Data size
Byte
Halfword
Word
Reserved
Debug in Depth
. In the
B-43