SAM7X512 Atmel Corporation, SAM7X512 Datasheet - Page 277

• Manufacturer Part Number: SAM7X512
• Manufacturer: Atmel Corporation

Specifications of SAM7X512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

IRQ
Joint Test Action Group
JTAG
Link register
Little-endian memory
LR
Macrocell
Memory Management Unit
MMU
PC
Privileged mode
Processor Status Register
Program Counter
Program Status Register
ARM DDI 0029G
Interrupt request.
The name of the organization that developed standard IEEE 1149.1. This standard
defines a boundary-scan architecture used for in-circuit testing of integrated circuit
devices.
See Joint Test Action Group.
This register holds the address of the next instruction after a branch with link
instruction.
Memory organization where the most significant byte of a word is at a higher address
than the least significant byte.
See Link register
A complex logic block with a defined interface and behavior. A typical VLSI system
will comprise several macrocells (such as an ARM7TDMI, an ETM7, and a memory
block) plus application-specific logic.
Allows control of a memory system. Most of the control is provided through translation
tables held in memory. The ARM7TDMI processor does not include a memory
management unit, but you can add one if required.
See Memory Management Unit
See Program Counter.
Any processor mode other than User mode. Memory systems typically check memory
accesses from privileged modes against supervisor access permissions rather than the
more restrictive user access permissions. The use of some instructions is also restricted
to privileged modes.
See Program Status Register
Register 15, the Program Counter, is used in most instructions as a pointer to the
instruction that is two instructions after the current instruction.
Contains some information about the current program and some information about the
current processor. Also referred to as Processor Status Register.
Copyright © 1994-2001. All rights reserved.
Glossary-3
Glossary