SAM7X512 Atmel Corporation, SAM7X512 Datasheet
SAM7X512
Specifications of SAM7X512
Related parts for SAM7X512
SAM7X512 Summary of contents
Page 1
... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) • ...
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... VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector • Fully Static Operation MHz at 1.65V and 85° C Worst Case Conditions • Available in 100-lead LQFP Green and 100-ball TFBGA Green Packages SAM7X512/256/128 2 ® Infrared Modulation/Demodulation 2 C Compatible Devices Supported ...
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... Description Atmel's SAM7X512/256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components. ...
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... SAM7X512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADVREF SAM7X512/256/128 4 SAM7X512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK System Controller TST FIQ AIC ...
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... Input Flash Memory Input High Reset/Test I/O Input High Debug Unit Input Output AIC Input Input PIO I/O I/O SAM7X512/256/128 Comments 3V to 3.6V 1.85V 3.6V 1.65V to 1.95V 1.65V to 1.95V No pull-up resistor No pull-up resistor No pull-up resistor (1) Pull-down resistor (1) Pull-down resistor Pull-up resistor, Open Drain Low ...
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... Master In Slave Out SPIx_MOSI Master Out Slave In SPIx_SPCK SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select TWD Two-wire Serial Data TWCK Two-wire Serial Clock SAM7X512/256/128 6 Active Type USB Device Port Analog Analog USART I/O I/O Input Output Input ...
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... Input Input Output Output Output Input Input Input Input Input Input Output I/O Output Considerations”. SAM7X512/256/128 Active Level Comments Digital pulled-up inputs at reset Analog Inputs High Low Low Low RMII only MII only MII only ETX0 - ETX1 only in RMII MII only ...
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... Package The SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-com- pliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section. Figure 4-1. SAM7X512/256/128 8 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip- 100-lead LQFP Package Outline (Top View) ...
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... PA25/PGMD13 PB15 60 PA26/PGMD14 PB17 61 VDDCORE 62 PB7 63 PB12 64 PB0 65 PB1 66 PB2 67 PB3 68 PB10 69 PB11 70 PA19/PGMD7 71 PA20/PGMD8 72 VDDIO 73 PA27/PGMD15 PA21/PGMD9 74 PA22/PGMD10 75 SAM7X512/256/128 TDI 76 GND 77 JTAGSEL PB16 78 PB4 PA0/PGMEN0 NRST 82 PA1/PGMEN1 TST VDDIO 86 VDDCORE 87 VDDCORE PB18 88 PA4/PGMNCMD PB19 89 PA5/PGMRDY PB20 90 PA6/PGMNOE PB21 ...
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... E4 B10 PA17/PGMD5 E5 C1 PB16 E6 C2 PB4 E7 C3 PB10 E8 C4 PB3 E9 C5 PB0 E10 SAM7X512/256/128 10 shows the orientation of the 100-ball TFBGA package. A detailed mechanical 100-ball TFBGA Package Outline (Top View BALL A1 Signal Name Pin Signal Name ...
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... Power Consumption The SAM7X512/256/128 has a static current of less than 60 µA on VDDCORE at 25°C, includ- ing the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. ...
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... Typical Powering Schematics The SAM7X512/256/128 supports a 3.3V single supply mode. The internal regulator input con- nected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. the power schematics to be used for USB bus-powered systems. Figure 5-1. SAM7X512/256/128 12 3.3V System Single Power Supply Schematic ...
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... SAM7X512/256/128 when asserted high. The TST pin integrates a permanent pull-down resis- tor of about 15 kΩ ...
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... I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. SAM7X512/256/128 14 6120I–ATARM–06-Apr-11 ...
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... Facilitates debug by detection of bad pointers • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors 6120I–ATARM–06-Apr-11 Controller SAM7X512/256/128 15 ...
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... One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements • Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest): SAM7X512/256/128 16 wait states Receive ...
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... Full chip erase time – 10,000 write cycles, 10-year data retention capability – 8 lock bits, each protecting 8 sectors of 64 pages – Protection Mode to secure contents of the Flash • 32 Kbytes of Fast SRAM – Single-cycle access at full speed 6120I–ATARM–06-Apr-11 SAM7X512/256/128 17 ...
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... Figure 8-1. SAM7X512/256/128 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF SAM7X512/256/128 18 Internal Memory Mapping 0x0000 0000 Boot Memory (1) ...
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... After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The SAM7X512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA program. 8.4.3 Internal Flash • ...
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... Embedded Flash 8.5.1 Flash Overview • The Flash of the SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the SAM7X256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. ...
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... Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.4 Security Bit Feature The SAM7X512/256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command “ ...
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... The SAM-BA Boot is in ROM and is mapped at address 0x0 when the GPNVM Bit 2 is set to 0. When GPNVM bit 2 is set to 1, the device boots from the Flash. When GPNVM bit 2 is set to 0, the device boots from ROM (SAM-BA). SAM7X512/256/128 22 6120I–ATARM–06-Apr-11 ...
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... F000 and 0xFFFF FFFF. Figure 9-1 on page 24 Figure 8-1 on page 18 erals. Note that the Memory Controller configuration user interface is also mapped within this address space. 6120I–ATARM–06-Apr-11 shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller periph- SAM7X512/256/128 23 ...
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... Figure 9-1. NRST XOUT PLLRC PA0-PA30 PB0-PB30 SAM7X512/256/128 24 System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset Timer SLCK Real-Time Timer power_on_reset ...
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... Brownout Detector and Power-on Reset The SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. ...
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... RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. SAM7X512/256/128 26 Clock Generator Block Diagram Clock Generator Embedded RC ...
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... Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4,...,/64 PLLCK Programmable Clock Controller SLCK MAINCK PLLCK /1,/2,/4,...,/64 USB Clock Controller ON/OFF Divider PLLCK /1,/2,/4 sources SAM7X512/256/128 Processor PCK Clock Controller int Idle Mode MCK Peripherals periph_clk[2..18] Clock Controller ON/OFF Prescaler pck[0..3] UDPCK 27 ...
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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x275C 0A40 (MRL A) for SAM7X512 – Chip ID is 0x275B 0940 (MRL for SAM7X256 – Chip ID is 0x275B 0942 (MRL C) for SAM7X256 – ...
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... Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 6120I–ATARM–06-Apr-11 SAM7X512/256/128 29 ...
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... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 Peripheral Identifiers The SAM7X512/256/128 embeds a wide range of peripherals. Identifiers of the SAM7X512/256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID 0 ...
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... Peripheral Multiplexing on PIO Lines The SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func- tions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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... PA19 CANRX PA20 CANTX PA21 TF PA22 TK PA23 TD PA24 RD PA25 RK PA26 RF PA27 DRXD PA28 DTXD PA29 FIQ PA30 IRQ0 SAM7X512/256/128 32 Peripheral B Comments High-Drive High-Drive SPI1_NPCS1 High-Drive SPI1_NPCS2 High-Drive SPI1_NPCS3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 PCK1 IRQ1 TCLK2 SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 PCK3 ...
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... TIOB2 PB29 PCK1 PB30 PCK2 6120I–ATARM–06-Apr-11 Peripheral B Comments PCK0 SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 RI1 PWM0 AD0 PWM1 AD1 PWM2 AD2 PWM3 AD3 SAM7X512/256/128 Application Usage Function Comments 33 ...
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... Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency Master Clock 10.8 Two-wire Interface • Master Mode only • Compatibility with I SAM7X512/256/128 34 peripherals Sensors between clock and data 2 C compatible devices (refer to the TWI section of the datasheet) ® ...
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... Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.11 Timer Counter • Three 16-bit Timer Counter Channels – Two output compare or one input capture per channel • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement 6120I–ATARM–06-Apr-11 SAM7X512/256/128 35 ...
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... Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 256 bytes ping-pong – Ping-pong Mode (two memory banks) for bulk endpoints • Suspend/resume logic SAM7X512/256/128 36 Table 10-4 Timer Counter Clocks Assignment Clock MCK/2 MCK/8 ...
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... Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Four of eight analog inputs shared with digital signals 6120I–ATARM–06-Apr-11 enabled channels SAM7X512/256/128 37 ...
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... SAM7X512/256/128 38 6120I–ATARM–06-Apr-11 ...
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... ARM – Thumb • Three-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 6120I–ATARM–06-Apr-11 ® High-performance 32-bit Instruction Set ® High Code Density 16-bit Instruction Set SAM7X512/256/128 ® ® and 16-bit Thumb instruction sets, allow- 39 ...
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... At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer. SAM7X512/256/128 40 6120I–ATARM–06-Apr-11 ...
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... R10 R10 R11 R11 R12 R12 R13_SVC R13_ABORT R14_SVC R14_ABORT PC PC CPSR CPSR SPSR_SVC SPSR_ABORT SAM7X512/256/128 Undefined Interrupt Fast Interrupt Mode Mode Mode ...
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... Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 11-2 SAM7X512/256/128 42 supports five types of exception and a privileged processing mode for each type. gives the ARM instruction mnemonic list. 6120I–ATARM–06-Apr-11 ...
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... Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor SAM7X512/256/128 Mnemonic Operation CDP Coprocessor Data Processing MVN Move Not ADC Add with Carry SBC ...
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... TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH SAM7X512/256/128 44 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply ...
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... A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram PDC 6120I–ATARM–06-Apr-11 ICE/JTAG Boundary TAP TAP ICE ARM7TDMI DBGU SAM7X512/256/128 TMS TCK TDI JTAGSEL TDO POR Reset and Test TST DTXD DRXD 45 ...
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... Application Examples 12.3.1 Debug Environment Figure 12-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example SAM7X512/256/128 46 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 AT91SAMSxx Connector AT91SAM7Sxx-based Application Board ...
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... Microcontroller Reset Test Mode Select ICE and JTAG Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Debug Unit Debug Receive Data Debug Transmit Data SAM7X512/256/128 Tester Chip 2 Chip 1 Type Active Level Input/Output Input Input Input Output Input ...
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... A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM7X512 Debug Unit Chip ID value is 0x275C 0A40 on 32-bit width. The SAM7X256 Debug Unit Chip ID value is 0x275B 0940 on 32-bit width. The SAM7X128 Debug Unit Chip ID value is 0x275A 0740 on 32-bit width. ...
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... PA3/RTS0/SPI1_NPCS2 176 175 174 PA2/SCK0/SPI1_NPCS1 173 172 171 PA4/CTS0/SPI1_NPCS3 170 169 168 PA5/RXD1 167 166 165 PA6/TXD1 164 SAM7X512/256/128 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-2. Number SAM7X512/256/128 50 SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 163 162 PA7/SCK1/SPI0_NPCS1 161 160 ERASE 159 158 PB27/TIOA2/PWM0/AD0 157 156 155 PB28/TIOB2/PWM1/AD1 154 153 152 PB29/PCK1/PWM2/AD2 151 150 149 PB30/PCK2/PWM3/AD3 148 147 146 PA8/RTS1/SPI0_NPCS2 145 144 143 PA9/CTS1/SPI0_NPCS3 ...
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... PB8/EMDC 109 108 107 PB14/ERX3/SPI0_NPCS2 106 105 104 PB13/ERX2/SPI0_NPCS1 103 102 101 PB6/ERX1 100 99 98 PB5/ERX0 97 SAM7X512/256/128 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT ...
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... Table 12-2. Number SAM7X512/256/128 52 SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 96 95 PB15/ERXDV/ECRSDV PB17/ERXCK/SPI0_NPCS3 PB7/ERXER PB12/ETXER/TCLK0 PB0/ETXCK/EREFCK/PCK0 PB1/ETXEN PB2/ETX0 PB3/ETX1 PB10/ETX2/SPI1_NPCS1 PB11/ETX3/SPI1_NPCS2 PA19/CANRX 64 Associated BSR Pin Type Cells INPUT IN/OUT ...
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... PA23/TD/SPI1_MOSI PA24/RD/SPI1_MISO PA25/RK/SPI1_NPCS1 PA26/RF/SPI1_NPCS2 PB18/EF100/ADTRG PB19/PWM0/TCLK1 31 SAM7X512/256/128 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-2. Number SAM7X512/256/128 54 SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 30 29 PB20/PWM1/PCK0 PB21/PWM2/PCK2 PB22/PWM3/PCK2 PB23/TIOA0/DCD1 PB24/TIOB0/DSR1 PB25/TIOA1/DTR1 PB26/TIOB1/RI1 PA27DRXD/PCK3 PA28/DTXD PA29/FIQ/SPI1_NPCS3 1 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL ...
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... PART NUMBER[27:12]: Product Part Number AT91SAM7X512: 0x5B18 AT91SAM7X256: 0x5B17 AT91SAM7X128: 0x5B16 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. AT91SAM7X512: JTAG ID Code value is 05B1_803F AT91SAM7X256: JTAG ID Code value is 05B1_703F AT91SAM7X128: JTAG ID Code value is 05B1_603F 6120I–ATARM–06-Apr- ...
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... SAM7X512/256/128 56 6120I–ATARM–06-Apr-11 ...
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... A brownout detection is also available to prevent the processor from falling into an unpredictable state. 13.1 Block Diagram Figure 13-1. Reset Controller Block Diagram Main Supply 6120I–ATARM–06-Apr-11 Reset Controller bod_rst_en Brownout Manager brown_out Startup POR Counter NRST NRST Manager nrst_out WDRPROC wd_fault SAM7X512/256/128 bod_reset Reset State rstc_irq Manager proc_nreset user_reset periph_nreset exter_nreset SLCK 57 ...
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... As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset so, the bit URSTIEN in RSTC_MR must be written at 1. SAM7X512/256/128 58 Figure 13-2 shows the block diagram of the NRST Manager. ...
Page 59
... The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 13-3. Brownout Manager 6120I–ATARM–06-Apr-11 Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs bod_rst_en RSTC_SR brown_out BODSTS SAM7X512/256/128 bod_reset RSTC_MR BODIEN rstc_irq Other interrupt sources 59 ...
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... When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately. Figure 13-4. Power-up Reset SLCK MCK Main Supply POR output proc_nreset periph_nreset NRST (nrst_out) SAM7X512/256/128 60 Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator Startup Time Processor Startup = 3 cycles EXTERNAL RESET LENGTH = 2 cycles Any Freq. ...
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... NRST (nrst_out) 6120I–ATARM–06-Apr- Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH SAM7X512/256/128 Processor Startup = 3 cycles 0x4 = User Reset ...
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... Brownout Reset. Figure 13-6. Brownout Reset State SLCK Any MCK Freq. brown_out or bod_reset proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) SAM7X512/256/128 62 Resynch. Processor Startup 2 cycles = 3 cycles XXX 0x5 = Brownout Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 6120I–ATARM–06-Apr-11 ...
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... As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 63 ...
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... Figure 13-7. Software Reset SAM7X512/256/128 64 SLCK Any MCK Freq. Write RSTC_CR Resynch. 1 cycle proc_nreset if PROCRST=1 RSTTYP Any periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 SRCMP in RSTC_SR Processor Startup = 3 cycles XXX 0x3 = Software Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 6120I–ATARM–06-Apr-11 ...
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... When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 13-8. Watchdog Reset Only if WDRPROC = 0 6120I–ATARM–06-Apr-11 SLCK Any MCK Freq. wd_fault proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) SAM7X512/256/128 Processor Startup = 3 cycles XXX 0x2 = Watchdog Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 65 ...
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... A watchdog event has priority over the current state. – The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. SAM7X512/256/128 66 proc_nreset signal. 6120I–ATARM–06-Apr-11 ...
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... Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. Figure 13-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 6120I–ATARM–06-Apr-11 SAM7X512/256/128 read RSTC_SR 2 cycle resynchronization Figure 67 ...
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... Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register SAM7X512/256/128 68 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset - 0x0000_0000 0x0000_0000 6120I–ATARM–06-Apr-11 ...
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... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6120I–ATARM–06-Apr- KEY – – – – – – – – EXTRST SAM7X512/256/128 – – – PERRST – PROCRST 24 16 – 8 – ...
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... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. SAM7X512/256/128 – ...
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... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6120I–ATARM–06-Apr- KEY – – – – – URSTIEN – SAM7X512/256/128 – – BODIEN ERSTL – – URSTEN (ERSTL+1) Slow Clock cycles. This ...
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... SAM7X512/256/128 72 6120I–ATARM–06-Apr-11 ...
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... RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV SAM7X512/256/128 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 73 ...
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... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface SAM7X512/256/128 74 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 75
... Real-time Timer (RTT) User Interface Table 14-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6120I–ATARM–06-Apr-11 SAM7X512/256/128 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only Reset Value 0x0000_8000 0xFFFF_FFFF ...
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... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. SAM7X512/256/128 – ...
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... CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6120I–ATARM–06-Apr- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV SAM7X512/256/128 ...
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... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. SAM7X512/256/128 – ...
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... Block Diagram Figure 15-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6120I–ATARM–06-Apr-11 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR SAM7X512/256/128 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT PICNT PIT_MR PITIEN pit_irq 79 ...
Page 80
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. SAM7X512/256/128 80 Figure 15-2 illustrates 6120I– ...
Page 81
... Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6120I–ATARM–06-Apr-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR SAM7X512/256/128 APB cycle APB cycle restarts MCK Prescaler ...
Page 82
... Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register SAM7X512/256/128 82 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset 0x000F_FFFF 0x0000_0000 ...
Page 83
... PIV PIV – – – – – – – – – – – – SAM7X512/256/128 – PITIEN PITEN PIV – – – – – – – ...
Page 84
... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAM7X512/256/128 PICNT ...
Page 85
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6120I–ATARM–06-Apr-11 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset SAM7X512/256/128 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 85 ...
Page 86
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. SAM7X512/256/128 86 6120I–ATARM–06-Apr-11 ...
Page 87
... Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6120I–ATARM–06-Apr-11 Watchdog Error WDT_CR = WDRSTT SAM7X512/256/128 Watchdog Underflow if WDRSTEN WDRSTEN ...
Page 88
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM7X512/256/128 88 Name WDT_CR WDT_MR WDT_SR KEY – ...
Page 89
... The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6120I–ATARM–06-Apr- WDDBGHLT WDD WDFIEN WDV SAM7X512/256/128 WDD WDV ...
Page 90
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. SAM7X512/256/128 – ...
Page 91
... Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset wake up the Voltage Regulator in Normal Mode. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 91 ...
Page 92
... Read-write 31 30 – – – – – – – – • PSTDBY: Periodic Interval Value 0 = Voltage regulator in normal mode Voltage regulator in standby mode (low-power mode). SAM7X512/256/128 92 Name VREG_MR – – – – – – – ...
Page 93
... Processor Abort EMAC DMA Peripheral DMA Controller 6120I–ATARM–06-Apr-11 Memory Controller ASB Abort Status Address Misalignment Decoder Bus Detector Arbiter User Interface APB Bridge Peripheral 0 APB Peripheral 1 Peripheral N SAM7X512/256/128 Embedded Internal Flash Flash Controller Internal RAM From Master to Slave 93 ...
Page 94
... One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed Figure 18-2 Figure 18-2. Memory Areas SAM7X512/256/128 94 shows the assignment of the 256-Mbyte memory areas. 0x0000 0000 256M Bytes 0x0FFF FFFF ...
Page 95
... FFFF Internal Flash 0x0020 0000 Internal Memory Area 2 256M Bytes Internal SRAM 0x002F FFFF 0x0030 0000 Internal Memory Area 3 Internal ROM 0x003F FFFF 0x0040 0000 Undefined Areas 0x0FFF FFFF SAM7X512/256/128 1 M Bytes 1 M Bytes 1 M Bytes 1 M Bytes 252 M Bytes (Abort) 95 ...
Page 96
... Note that the accesses of the ARM processor when it is fetching instructions are not checked. SAM7X512/256/128 96 6120I–ATARM–06-Apr-11 ...
Page 97
... As the requested address is saved in the Abort Status Register and the address of the instruc- tion generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 97 ...
Page 98
... MC Abort Status Register 0x08 MC Abort Address Status Register 0x10-0x5C Reserved 0x60 EFC0 Configuration Registers (1) 0x70 EFC1 Configuration Registers Note: 1. EFC1 pertains to AT91SAM7X512 only. SAM7X512/256/128 98 Name Access MC_RCR Write-only MC_ASR Read-only MC_AASR Read-only See the Embedded Flash Controller Section Reset State ...
Page 99
... This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 6120I–ATARM–06-Apr- – – – – – – – – – – – – SAM7X512/256/128 – – – – – – – – – – – RCB 99 ...
Page 100
... ABTTYP: Abort Type Status ABTTYP • MST_EMAC: EMAC Abort Source 0: The last aborted access was not due to the EMAC. 1: The last aborted access was due to the EMAC. SAM7X512/256/128 100 – – – – – ...
Page 101
... SVMST_ARM: Saved ARM Abort Source 0: No abort due to the ARM occurred since the last read of MC_ASR notified in the bit MST_ARM least one abort due to the ARM occurred since the last read of MC_ASR. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 101 ...
Page 102
... MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 • ABTADD: Abort Address This field contains the address of the last aborted access. SAM7X512/256/128 102 ABTADD ABTADD ABTADD ABTADD 26 ...
Page 103
... Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM bits. The Security and GPNVM bits embedded only on EFC0 apply to the two blocks in the AT91SAM7X512 ...
Page 104
... The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. SAM7X512/256/128 104 Flash Memory ...
Page 105
... Bytes 4-7 Bytes 8-11 Bytes 4-7 Bytes 0-3 Bytes 2-3 Bytes 4-5 Bytes 6-7 1 Wait State Cycle @Byte 2 @Byte 4 @Byte 6 Bytes 0-3 Bytes 4-7 Bytes 0-3 Bytes 0-1 Bytes 2-3 Bytes 4-5 SAM7X512/256/128 @Byte 14 @Byte 10 @Byte 12 Bytes 12-15 Bytes 8-11 Bytes 12-15 Bytes 8-9 Bytes 10-11 Bytes 12-13 1 Wait State Cycle 1 Wait State Cycle @Byte 12 @Byte 8 @Byte 10 Bytes 12-15 Bytes 8-11 Bytes 4-7 ...
Page 106
... Flash erasing. Table 19-2. Command Write page Set Lock Bit Write Page and Lock Clear Lock Bit Erase all Set General-purpose NVM Bit Clear General-purpose NVM Bit Set Security Bit SAM7X512/256/128 106 3 Wait State Cycles 3 Wait State Cycles @ Bytes 4-7 Bytes 0-3 0-1 ...
Page 107
... When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 107 ...
Page 108
... NEBP bit in the MC_FMR register before writing the command in the MC_FCR register. By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased before (see SAM7X512/256/128 108 Read Status: MC_FSR No ...
Page 109
... ... Step 2. Programming of the second part of Page 7 (NEBP = 1) Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. SAM7X512/256/128 32 bits wide ... ... ...
Page 110
... The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in MC_FSR reads 1. Note: SAM7X512/256/128 110 Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed. 6120I–ATARM–06-Apr-11 ...
Page 111
... The goal of the security bit is to prevent external access to the internal bus system. (Does not apply to EFC1 on the AT91SAM7X512.) JTAG, Fast Flash Programming and Flash Serial Test Interface features are disabled. Once set, this bit can be reset only by an external hardware ERASE request to the chip ...
Page 112
... When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the security bit is active, the SECURITY bit in the MC_FSR is set. SAM7X512/256/128 112 6120I–ATARM–06-Apr-11 ...
Page 113
... Embedded Flash Controller (EFC ) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register Mapping tables and Reg- ister descriptions that follow. ...
Page 114
... NEBP: No Erase Before Programming 0: A page erase is performed before programming erase is performed before programming. • FWS: Flash Wait State This field defines the number of wait states for read and write operations: FWS SAM7X512/256/128 114 – – – ...
Page 115
... When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds. Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN) must be correctly programmed. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 115 ...
Page 116
... FCMD: Flash Command This field defines the Flash commands: FCMD 0000 0001 0010 0011 0100 1000 1011 1101 1111 Others SAM7X512/256/128 116 KEY – – – PAGEN – – Operations No command ...
Page 117
... This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is writ- ten with a different value, the write is not performed and no action is started. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 PAGEN Description PAGEN defines the page number to be written. ...
Page 118
... SECURITY: Security Bit Status (Does not apply to EFC1 on the AT91SAM7X512.) 0: The security bit is inactive. 1: The security bit is active. • GPNVMx: General-purpose NVM Bit Status (Does not apply to EFC1 on the AT91SAM7X512.) 0: The corresponding general-purpose NVM bit is inactive. 1: The corresponding general-purpose NVM bit is active. ...
Page 119
... Other pins must be left unconnected. Figure 20-1. Parallel Programming Interface 6120I–ATARM–06-Apr-11 TST VDDIO PGMEN0 VDDIO VDDIO PGMEN1 NCMD PGMNCMD RDY PGMRDY NOE PGMNOE NVALID PGMNVALID PGMM[3:0] MODE[3:0] DATA[15:0] PGMD[15: 50MHz XIN SAM7X512/256/128 VDDCORE VDDIO VDDPLL VDDFLASH GND 119 ...
Page 120
... Depending on the MODE settings, DATA is latched in different internal registers. Table 20-2. MODE[3:0] 0000 0001 0010 0101 Default When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. SAM7X512/256/128 120 Type Power Power Power Power Power Ground Clocks Input ...
Page 121
... GGPB SSE GSE WRAM SEFC GVE 1. Applies to AT91SAM7X512 external clock is available. POR_RESET POR_RESET After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal external clock ( > 32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake ...
Page 122
... Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal 6 Waits for RDY high 20.2.4.2 Read Handshaking For details on the read handshaking sequence, refer to Figure 20-3. SAM7X512/256/128 122 NCMD 2 3 RDY NOE NVALID DATA[15:0] 1 MODE[3:0] Device Action Waits for NCMD low ...
Page 123
... Write handshaking ADDR1 Read handshaking DATA Read handshaking DATA ... ... Write handshaking ADDR0 Write handshaking ADDR1 Read handshaking DATA Read handshaking DATA ... ... SAM7X512/256/128 DATA I/O Input Input Input Input Tristate Output Output Output Output X Input Input Input DATA[15:0] READ Memory Address LSB Memory Address ...
Page 124
... This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 20-9. Step 1 2 SAM7X512/256/128 124 Write Command Handshake Sequence MODE[3:0] Write handshaking CMDE ...
Page 125
... Handshake Sequence Write handshaking Write handshaking Handshake Sequence Write handshaking Read handshaking Handshake Sequence Write handshaking Write handshaking Handshake Sequence Write handshaking Read handshaking SAM7X512/256/128 MODE[3:0] DATA[15:0] CMDE SLB or CLB DATA Bit Mask th lock bit is active when the bit MODE[3:0] DATA[15:0] CMDE ...
Page 126
... Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The AT91SAM7X512 security bit is controlled by the EFC0. To use the Set Security Bit com- mand, the EFC0 must be selected using the Select EFC command Table 20-14 ...
Page 127
... Handshake Sequence MODE[3:0] ... ... Write handshaking ADDR0 Write handshaking ADDR1 Write handshaking DATA Write handshaking DATA ... ... Handshake Sequence Write handshaking Write handshaking SAM7X512/256/128 DATA[15:0] ... Memory Address LSB Memory Address *Memory Address++ *Memory Address++ ... MODE[3:0] DATA[15:0] CMDE GVE DATA Version 127 ...
Page 128
... I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground Main Clock Input. This input can be tied to GND. In this XIN case, the device is clocked by the internal RC oscillator. SAM7X512/256/128 128 VDDIO TST VDDIO PGMEN0 VDDIO PGMEN1 TDI TDO TMS TCK ...
Page 129
... Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer handshake. TDI TMS SAM7X512/256/128 Active Level Comments High Must be connected to VDDIO. High Must be connected to VDDIO High Must be connected to VDDIO - Pulled-up input at reset - Pulled-up input at reset - - Pulled-up input at reset ) if an external clock is available. ...
Page 130
... Table 20-3 on page is reading and writing the Debug Comms Registers. 20.3.4.1 Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at SAM7X512/256/128 130 r/w 4 Address 0 ...
Page 131
... DR Data (Number of Words to Read) << READ Address Memory [address] Memory [address+4] ... Memory [address+(Number of Words to Read - 1 Data (Number of Words to Write) << (WP or WPL or EWP or EWPL) Address Memory [address] Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1)* 4] SAM7X512/256/128 131 ...
Page 132
... GP NVM bits can be read using Get GPNVM Bit command (GGPB). When a bit set in the Bit Mask is returned, then the corresponding GPNVM bit is set. Table 20-26. Get General-purpose NVM Bit Command Read/Write Write Read SAM7X512/256/128 132 DR Data EA DR Data SLB or CLB Bit Mask ...
Page 133
... Fast Flash programming is disabled. No other command can be run. Only an event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The AT91SAM7X512 security bit is controlled by the EFC0. To use the Set Security Bit com- mand, the EFC0 must be selected using the Select EFC command. ...
Page 134
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-30. Get Version Command Read/Write Write Read SAM7X512/256/128 134 DR Data GVE Version 6120I–ATARM–06-Apr-11 ...
Page 135
... Jump to SAM-BA Boot sequence (see 6120I–ATARM–06-Apr-11 ® Boot is then executed. It waits for transactions either on the USB device the Device USB Enumeration Setup Successful ? Run SAM-BA Boot SAM7X512/256/128 Figure 21- AutoBaudrate Sequence Successful ? Yes Yes Run SAM-BA Boot “ ...
Page 136
... The SAM-BA boot principle is to: – Check if USB Device enumeration has occurred – Check if the AutoBaudrate sequence has succeeded (see Figure 21-2. AutoBaudrate Flow Diagram – Once the communication interface is identified, the application runs in an infinite SAM7X512/256/128 136 Device Setup Character '0x80' ...
Page 137
... Address, NbOfBytes# go Address# display version No argument There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. : Number of bytes in hexadecimal to receive NbOfBytes SAM7X512/256/128 Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# ...
Page 138
... The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. SAM7X512/256/128 138 to 01) shows a transmission using this protocol. ...
Page 139
... Used to clear or disable a specific feature. Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. SAM7X512/256/128 139 ...
Page 140
... Hardware and Software Constraints • SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 122880 bytes for SAM7x512, 57344 bytes for SAM7X256 and 24576 bytes for SAM7X128. ...
Page 141
... The peripheral triggers PDC transfers using transmit and receive signals. When the pro- grammed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. 22.2 Block Diagram Figure 22-1. Block Diagram 6120I–ATARM–06-Apr-11 Peripheral DMA Controller Peripheral THR PDC Channel 0 PDC Channel 1 RHR Status & Control Control SAM7X512/256/128 Memory Control Controller 141 ...
Page 142
... If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag. If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. SAM7X512/256/128 142 6120I–ATARM–06-Apr-11 ...
Page 143
... If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 143 ...
Page 144
... PDC Transfer Status Register Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.). SAM7X512/256/128 144 Name (1) PERIPH _RPR ...
Page 145
... RXCTR: Receive Counter Value Number of receive transfers to be performed. 6120I–ATARM–06-Apr- RXPTR RXPTR RXPTR RXPTR RXCTR RXCTR SAM7X512/256/128 145 ...
Page 146
... PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read-write • TXCTR: Transmit Counter Value TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral DMA transfer is stopped. SAM7X512/256/128 146 TXPTR TXPTR TXPTR 5 ...
Page 147
... RXNCR: Receive Next Counter Value RXNCR is the size of the next buffer to receive. 6120I–ATARM–06-Apr- RXNPTR RXNPTR RXNPTR RXNPTR RXNCR RXNCR SAM7X512/256/128 147 ...
Page 148
... TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 22.4.8 PDC Transmit Next Counter Register Register Name: PERIPH_TNCR Access Type: Read-write • TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit. SAM7X512/256/128 148 TXNPTR TXNPTR TXNPTR ...
Page 149
... Disables the transmitter PDC transfer requests 6120I–ATARM–06-Apr- – – – – – – – – – – – – SAM7X512/256/128 – – – – – – – TXTDIS TXTEN – RXTDIS RXTEN 149 ...
Page 150
... RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled Receiver PDC transfer requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled Transmitter PDC transfer requests are enabled. SAM7X512/256/128 150 – – – ...
Page 151
... The fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt. 23.2 Block Diagram Figure 23-1. Block Diagram 6120I–ATARM–06-Apr-11 FIQ AIC IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded Peripheral Embedded Peripheral APB SAM7X512/256/128 ARM Processor nFIQ nIRQ 151 ...
Page 152
... Figure 23-2. Description of the Application Block 23.4 AIC Detailed Block Diagram Figure 23-3. AIC Detailed Block Diagram 23.5 I/O Line Description Table 23-1. I/O Line Description Pin Name FIQ IRQ0 - IRQn SAM7X512/256/128 152 Standalone OS Drivers Applications General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals Advanced Interrupt Controller FIQ PIO ...
Page 153
... The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 153 ...
Page 154
... The AIC_ISR register reads the number of the current interrupt (see 158) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. SAM7X512/256/128 154 (See “Priority Controller” on page 158.) The automatic clear reduces See “ ...
Page 155
... AIC_SMRI (SRCTYPE) Level/ Source i Edge Edge Detector Set Clear AIC_ISCR AIC_ICCR AIC_SMRi SRCTYPE High/Low Pos./Neg. Edge Detector Set Clear SAM7X512/256/128 AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR FF AIC_IDCR Level/ AIC_IPR Edge AIC_IMR FF Fast Interrupt Controller or Priority Controller AIC_IECR AIC_IDCR ...
Page 156
... For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 23.7.2.1 External Interrupt Edge Triggered Source Figure 23-6. SAM7X512/256/128 156 External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ ...
Page 157
... Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active SAM7X512/256/128 157 ...
Page 158
... This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus acces- sible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR SAM7X512/256/128 158 PC,[PC,# -&F20] 6120I–ATARM–06-Apr-11 ...
Page 159
... For example, the instruction SUB PC, LR, #4 may be used. 6120I–ATARM–06-Apr-11 priority. The current level is the priority level of the current interrupt. must be read in order to de-assert nIRQ. SAM7X512/256/128 159 ...
Page 160
... PC. This has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: SAM7X512/256/128 160 If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur- ing this phase. ...
Page 161
... ARM core adjusts R14_fiq, decre- menting it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- 6120I–ATARM–06-Apr-11 PC,[PC,# -&F20] SAM7X512/256/128 161 ...
Page 162
... Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). SAM7X512/256/128 162 The “F” bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted ...
Page 163
... Automatic Clear Source n Input Stage Automatic Clear 6120I–ATARM–06-Apr-11 AIC_IPR AIC_IMR Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR AIC_IPR AIC_IMR Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. SAM7X512/256/128 nFIQ Priority Manager nIRQ 163 ...
Page 164
... AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: • An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. SAM7X512/256/128 164 6120I–ATARM–06-Apr-11 ...
Page 165
... Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. 6120I–ATARM–06-Apr-11 SAM7X512/256/128 165 ...
Page 166
... Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. SAM7X512/256/128 166 Name AIC_SMR0 ...
Page 167
... Internal Interrupt Sources High level Sensitive Positive edge triggered High level Sensitive Positive edge triggered SAM7X512/256/128 – – – – – – – – – PRIOR ...
Page 168
... The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. SAM7X512/256/128 168 29 28 ...
Page 169
... FIQV FIQV FIQV – – – – – – – – – – SAM7X512/256/128 – – – – – – – – – IRQID ...
Page 170
... Read-only Reset Value PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. SAM7X512/256/128 170 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 4 ...
Page 171
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM7X512/256/128 – – – – – – – – – – NIRQ NIFQ PID26 PID25 PID24 ...
Page 172
... AIC_ICCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Clear effect Clears corresponding interrupt. SAM7X512/256/128 172 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 4 ...
Page 173
... PID5 PID4 PID3 – – – – – – – – – – – – SAM7X512/256/128 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ – – – ...
Page 174
... PROT: Protection Mode 0 = The Protection Mode is disabled The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC The nIRQ and nFIQ lines are tied to their inactive state. SAM7X512/256/128 174 SIVR 21 ...
Page 175
... PID5 PID4 PID3 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM7X512/256/128 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS – PID26 PID25 PID24 ...
Page 176
... PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt The Fast Forcing feature is enabled on the corresponding interrupt. SAM7X512/256/128 176 PID29 PID28 PID27 PID21 PID20 PID19 13 ...
Page 177
... However, the Clock Generator registers are named CKGR_. shows the Main Oscillator block diagram. MOSCEN XIN Main Oscillator XOUT OSCOUNT Main SLCK Oscillator Slow Clock Counter Main Clock Frequency Counter SAM7X512/256/128 MAINCK Main Clock MOSCS MAINF MAINRDY MHz fundamental Figure 24-2. For further details on the elec- 177 ...
Page 178
... Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of SAM7X512/256/128 178 AT91SAM7X Microcontroller ...
Page 179
... PLL block. DIV Divider MAINCK SLCK PLLRC GND SAM7X512/256/128 MUL OUT PLL PLLCK PLLRC PLLCOUNT PLL LOCK Counter PLL Figure 179 ...
Page 180
... The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. SAM7X512/256/128 180 6120I–ATARM–06-Apr-11 ...
Page 181
... This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Figure 25-1. Master Clock Controller MAINCK PLLCK 6120I–ATARM–06-Apr-11 PMC_MCKR PMC_MCKR CSS SLCK Master Clock Prescaler SAM7X512/256/128 PRES MCK To the Processor Clock Controller (PCK) 181 ...
Page 182
... In order to stop a peripheral recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data cor- ruption or erroneous behavior of the system. SAM7X512/256/128 182 USBDIV USB ...
Page 183
... This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles. 6120I–ATARM–06-Apr-11 write_register(CKGR_MOR,0x00000701) SAM7X512/256/128 183 ...
Page 184
... MCKRDY has been enabled in the PMC_IER register. The PMC_MCKR register must not be programmed in a single write operation. The pre- ferred programming sequence for the PMC_MCKR register is as follows: SAM7X512/256/128 184 write_register(CKGR_PLLR,0x00040805) 6120I–ATARM–06-Apr-11 ...
Page 185
... CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For fur- Section 25.8.2 ther information, see SAM7X512/256/128 “Clock Switching Waveforms” on page 187 . . 185 ...
Page 186
... Depending on the system used, 15 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. SAM7X512/256/128 186 Each enabled peripheral clock corresponds to Master Clock. 6120I–ATARM–06-Apr-11 ...
Page 187
... Main Clock + 4.5 x SLCK 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock SAM7X512/256/128 SLCK PLL Clock 3 x PLL Clock + 4 x SLCK + 4 x SLCK + 2.5 x Main Clock 1 x Main Clock 3 x PLL Clock + – SLCK 2 ...
Page 188
... Figure 25-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR Figure 25-5. Change PLL Programming Write CKGR_PLLR SAM7X512/256/128 188 Slow Clock Main Clock MCKRDY Master Clock Main Clock PLL Clock LOCK MCKRDY Master Clock Main Clock 6120I–ATARM–06-Apr-11 ...
Page 189
... Figure 25-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR 6120I–ATARM–06-Apr-11 PLL Clock PCKRDY PCKx Output PLL Clock is selected SAM7X512/256/128 PCKx is enabled PCKx is disabled 189 ...
Page 190
... Programmable Clock 0 Register 0x0044 Programmable Clock 1 Register ... ... 0x0060 Interrupt Enable Register 0x0064 Interrupt Disable Register 0x0068 Status Register 0x006C Interrupt Mask Register 0x0070 - 0x007C Reserved SAM7X512/256/128 190 Name Access PMC_SCER Write-only PMC_SCDR Write-only PMC _SCSR Read-only – – PMC _PCER Write-only PMC_PCDR ...
Page 191
... Enables the corresponding Programmable Clock output. 6120I–ATARM–06-Apr- – – – – – – – – PCK3 – – – SAM7X512/256/128 – – – – – – PCK2 PCK1 PCK0 – – – 191 ...
Page 192
... Disables the Processor clock. This is used to enter the processor in Idle Mode. • UDP: USB Device Port Clock Disable effect Disables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Disable effect Disables the corresponding Programmable Clock output. SAM7X512/256/128 192 – – ...
Page 193
... The corresponding Programmable Clock output is enabled. 6120I–ATARM–06-Apr- – – – – – – – – PCK3 – – – SAM7X512/256/128 – – – – – – PCK2 PCK1 PCK0 – – PCK 193 ...
Page 194
... PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Disable effect Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. SAM7X512/256/128 194 PID29 PID28 PID27 PID21 PID20 ...
Page 195
... PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 6120I–ATARM–06-Apr- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM7X512/256/128 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 – – 195 ...
Page 196
... When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set. Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag. • OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time. SAM7X512/256/128 196 – ...
Page 197
... MAINF value is not valid or the Main Oscillator is disabled The Main Oscillator has been enabled previously and MAINF value is available. 6120I–ATARM–06-Apr- – – – – – – MAINF MAINF SAM7X512/256/128 – – – – – MAINRDY 197 ...
Page 198
... MUL: PLL Multiplier 0 = The PLL is deactivated 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1. • USBDIV: Divider for USB Clock USBDIV SAM7X512/256/128 198 USBDIV – MUL ...
Page 199
... PRES CSS PRES SAM7X512/256/128 26 25 – – – – – – CSS Clock Source Selection Slow Clock is selected Main Clock is selected Reserved PLL Clock is selected. Processor Clock ...
Page 200
... CSS: Master Clock Selection CSS • PRES: Programmable Clock Prescaler SAM7X512/256/128 200 – – – – – – – – – – PRES ...