SAM9G20 Atmel Corporation, SAM9G20 Datasheet

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... Mode for General Purpose 2-wire UART Serial Communication ® ® ARM Thumb Processor ® Technology for Java ® Acceleration AT91 ARM Thumb ® Microcontrollers AT91SAM9G20 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6384DS–ATARM–13-Jan-10 ...

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... VDDIOP (Peripheral I/Os) – 3.0V to 3.6V for VDDUSB – 3.0V to 3.6V VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 217-ball LFBGA and 247-ball TFBGA RoHS-compliant Package AT91SAM9G20 Summary 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding 6384DS–ATARM–13-Jan-10 ...

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... The AT91SAM9G20 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ler. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface ...

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... AT91SAM9G20 Block Diagram Figure 2-1. AT91SAM9G20 Block Diagram AT91SAM9G20 Summary 4 Filter Filter 6384DS–ATARM–13-Jan-10 ...

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... TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection RTCK Return Test Clock 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Summary Type Power Supplies Power Power Power Power Power Power Power Power Ground Ground Ground ...

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... CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 - CFCS1 CompactFlash Chip Select Lines AT91SAM9G20 Summary 6 Type Reset/Test I/O Input Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input ...

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... SSC Transmit Data RD SSC Receive Data TK SSC Transmit Clock RK SSC Receive Clock TF SSC Transmit Frame Sync RF SSC Receive Frame Sync 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Summary Type NAND Flash Support Output Output Output Output Output SDRAM Controller Output Output Output Output ...

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... Transmit Coding Error ERXDV Receive Data Valid ERX0-ERX3 Receive Data ERXER Receive Error ECRS Carrier Sense and Data Valid ECOL Collision Detect EMDC Management Data Clock EMDIO Management Data Input/Output AT91SAM9G20 Summary 8 Type Timer/Counter - TCx Input I/O I/O Serial Peripheral Interface - SPIx_ I/O I/O I/O I/O Output Two-Wire Interface I/O ...

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... Note: No PLLRCA line present on the AT91SAM9G20. 4. Package and Pinout • The AT91SAM9G20 is available in a 217-ball mm, LFBGA package (0.8 mm pitch) (Figure • The AT91SAM9G20 is available in a 247-ball 1.1 mm, TFBGA Green package, , (0.5 mm pitch) 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9G20 Mechanical Charac- teristics” ...

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... H16 C14 HDMB H17 C15 NC J1 C16 VDDUSB J2 C17 SHDN RAS J10 AT91SAM9G20 Summary 10 Signal Name Pin Signal Name A5 J14 TDO GND J15 PB19 A10 J16 TDI GND J17 PB16 VDDCORE K1 PC24 GNDUSB K2 PC20 VDDIOM K3 D15 ...

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... TFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9G20 Mechanical Charac- teristics” of the product datasheet. Figure 4-2. 6384DS–ATARM–13-Jan-10 shows the orientation of the 247-ball TFBGA package. 247-ball TFBGA Package (Bottom View) Ball ...

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... PC4 J18 E16 PC5 K2 E18 PC7 K3 E19 PC6 K5 F2 PC22 K6 F3 PC23 K7 F5 PC20 AT91SAM9G20 Summary 12 Signal Name Pin Signal Name CFIOR/NBS1/NWR1 K10 GND SDA10 K11 VDDIOM NBS0/A0 K12 GND A6 K13 GND A12 K14 XOUT32 A15 K15 XIN32 BA1/A17 ...

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... Power Considerations 5.1 Power Supplies The AT91SAM9G20 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1 ...

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... All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers inte- grate a programmable pull-up resistor of 75 kΩ typical with the exception P31. For details, refer to the section “AT91SAM9G20 Electrical Characteristics”. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. ...

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... On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 7.2 Bus Matrix • 6-layer Matrix, handling requests from 6 masters • Programmable Arbitration strategy – Fixed-priority Arbitration 6384DS–ATARM–13-Jan-10 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9G20 Summary 15 ...

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... Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9G20 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...

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... USART4 Transmit Channel – USART3 Transmit Channel – USART2 Transmit Channel – USART1 Transmit Channel – USART0 Transmit Channel – SPI1 Transmit Channel 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Masters to Slaves Access Master 0 & 1 ARM926 Slave Instruction & Data Internal SRAM ...

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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins AT91SAM9G20 Summary 18 6384DS–ATARM–13-Jan-10 ...

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... Memories Figure 8-1. AT91SAM9G20 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI ...

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... REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details. AT91SAM9G20 Summary 20 Table 8-1, “Internal Memory Mapping,” on page 20 ...

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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. ...

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... Supported devices – Standard and Low-power SDRAM (Mobile SDRAM) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Datapath AT91SAM9G20 Summary 22 Figure 8-1 on page 19. 6384DS–ATARM–13-Jan-10 ...

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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 9-1 on page 24 Figure 8-1 on page 19 peripherals. 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Summary shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 23 ...

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... System Controller Block Diagram Figure 9-1. AT91SAM9G20 System Controller Block Diagram irq0-irq2 periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSCSEL SLOW XIN32 CLOCK OSC XOUT32 XIN MAIN OSC ...

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... The PLL A outputs 400-800 MHz clock – The PLL B outputs 100 MHz clock – Both integrate an input divider to increase output accuracy – PLL A and PLL B embed their own filters 6384DS–ATARM–13-Jan-10 reset, user reset or watchdog reset AT91SAM9G20 Summary 25 ...

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... Idle Mode, processor stopped waiting for an interrupt – Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, – Backup Mode, Main Power Supplies off, VDDBU powered by a battery AT91SAM9G20 Summary 26 Clock Generator Block Diagram OSCSEL ...

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... Four 32-bit backup general-purpose registers 9.10 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Power Management Controller Block Diagram Divider Master Clock Controller SLCK Prescaler Divider ...

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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 9.12 Chip Identification • Chip ID:0x019905A1 • JTAG ID: 0x05B2403F • ARM926 TAP ID:0x0792603F AT91SAM9G20 Summary 28 enabled processor Generator the ARM Processor’s ICE Interface ® ...

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... Peripheral Identifiers of the AT91SAM9G20. A peripheral identifier is AT91SAM9G20 Peripheral Identifiers (Continued) Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC ...

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... IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.3 Peripheral Signal Multiplexing on I/O Lines The AT91SAM9G20 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions ...

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... I/O I/O I/O I/O I/O I/O I/O ETXER I/O ETX2 I/O ETX3 I/O ERX2 I/O ERX3 I/O ERXCK I/O ECRS I/O ECOL I/O RXD4 I/O TXD4 I/O AT91SAM9G20 Summary Application Usage Power Supply Function VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP ...

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... DTR0 ISI_D4 PB25 RI0 ISI_D5 PB26 RTS0 ISI_D6 PB27 CTS0 ISI_D7 PB28 RTS1 ISI_PCK PB29 CTS1 ISI_VSYNC PB30 PCK0 ISI_HSYNC PB31 PCK1 ISI_MCK AT91SAM9G20 Summary 32 Application Usage Comments Reset State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP ...

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... NCS6 I/O IRQ2 I/O IRQ1 I/O SPI0_NPCS2 I/O SPI0_NPCS3 I/O SPI1_NPCS1 I/O SPI1_NPCS2 I/O SPI1_NPCS3 I/O I/O TCLK5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AT91SAM9G20 Summary Application Usage Power Supply Function VDDANA VDDANA VDDANA VDDANA VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM ...

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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection AT91SAM9G20 Summary 34 peripherals Sensors and data per chip select ...

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... Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9G20, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features ...

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... Endpoint 4 and 5: 512 bytes, ping-pong mode • Embedded pad pull-up AT91SAM9G20 Summary 36 TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See Figure 8-1, “AT91SAM9G20 Memory Mapping,” on page 19 addresses. for TC Block 0 and TC Block 1 base 6384DS–ATARM–13-Jan-10 ...

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... Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Summary 37 ...

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... Pacakge Drawing 11.1 217-ball LFBA Package Figure 11-1. 217-ball LFBGA Package Drawing AT91SAM9G20 Summary 38 6384DS–ATARM–13-Jan-10 ...

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... TFBGA Package Figure 11-2. 247-ball TFBGA Package Drawing 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Summary 39 ...

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... AT91SAM9G20 Ordering Information Table 12-1. AT91SAM9G20 Ordering Information MRL A Ordering Code MRL B Ordering Code AT91SAM9G20-CU AT91SAM9G20B-CU – AT91SAM9G20B-CFU AT91SAM9G20 Summary 40 Package Package Type Temperature Operating Range BGA217 Green BGA247 Green Industrial -40°C to 85°C Industrial -40°C to 85°C 6384DS–ATARM–13-Jan-10 ...

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... Memory Card spec v1.1. Signal Description, Table Table 3-1, Signal Description and Section 11. “Pacakge Section 11.2 “247-ball TFBGA Section 12. “AT91SAM9G20 Ordering Information” Table 12-1, “AT91SAM9G20 Ordering Information,” 6384BS Overview “Features” on page 1, Debug Unit (DBGU) updated. Section 10.4.3 “USART”, “Optional Manchester Encoding” added to list of USART features. ...

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