SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 22

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SAM9G20

Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G20

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
8.2
8.2.1
8.2.2
8.2.3
22
External Memories
AT91SAM9G20 Summary
External Bus Interface
Static Memory Controller
SDRAM Controller
The external memories are accessed through the External Bus Interface. Each Chip Select line
has a 256-Mbyte memory area assigned.
Refer to the memory map in
• Integrates three External Memory Controllers
• Additional logic for NAND Flash
• Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64MBytes linear)
• Up to 8 chip selects, Configurable Assignment:
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
• Multiple device adaptability
• Multiple Wait State Management
• Slow Clock mode supported
• Supported devices
• Numerous configurations supported
– Static Memory Controller
– SDRAM Controller
– ECC Controller
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
– Static Memory Controller on NCS6-NCS7
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
– Standard and Low-power SDRAM (Mobile SDRAM)
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Datapath
Figure 8-1 on page
19.
6384DS–ATARM–13-Jan-10

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