SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 113
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SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 113 of 284
- Download datasheet (2Mb)
4.4.5
ARM DDI 0029G
Coprocessor register transfer instructions
Execute stage
Decode stage
It is essential that any action taken by the coprocessor while it is busy-waiting is
idempotent. This means that the actions taken by the coprocessor must not corrupt the
state of the coprocessor, and must be repeatable with identical results. The coprocessor
can only change its own state once the instruction has been executed.
The ARM7TDMI processor usually returns from processing the interrupt to retry the
coprocessor instruction. Other coprocessor instructions can be executed before the
interrupted instruction is executed again.
The coprocessor register transfer instructions, MCR and MRC, are used to transfer data
between a register in the ARM7TDMI processor register bank and a register in the
coprocessor register bank. An example sequence for a coprocessor register transfer is
shown in Figure 4-2.
Fetch stage
D[31:0]
MCLK
nCPI
CPA
CPB
Caution
Copyright © 1994-2001. All rights reserved.
ADD
ADD
SUB
ADD
SUB
Figure 4-2 Coprocessor register transfer sequence
MCR
ADD
SUB
MCR
MCR
SUB
TST
TST
SUB
MCR
SUB
TST
DATA
Coprocessor Interface
SUB
TST
INSTR
SUB
4-9
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