SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 268
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SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 268 of 284
- Download datasheet (2Mb)
Debug in Depth
B.16
B-50
The debug status register
The debug status register is 5 bits wide. If it is accessed for a write, with the read/write
bit set, the status bits are written. If it is accessed for a read, with the read/write bit clear,
the status bits are read. The format of the debug status register is shown in Figure B-10.
The function of each bit in this register is as follows:
Bit 4
Bit 3
Bit 2
Bits 1:0
The structure of the debug control and status registers is shown in Figure B-11 on
page B-51.
TBIT
4
Copyright © 1994-2001. All rights reserved.
Enables TBIT to be read. This enables the debugger to determine
the processor state and therefore which instructions to execute.
Enables the debugger to determine if a memory access from the
debug state has completed.
Enables the state of the core interrupt enable signal, IFEN, to be
read. Enables the state of the NMREQ signal from the core,
synchronized to TCK, to be read. This enables the debugger to
determine that a memory access from the debug state has
completed.
Enable the values on the synchronized versions of DBGRQ and
DBGACK to be read.
cgenL
3
IFEN
2
Figure B-10 Debug status register format
DBGRQ
1
ARM DDI 0029G
DBGACK
0
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