SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 235
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SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 235 of 284
- Download datasheet (2Mb)
ARM DDI 0029G
•
For input cells, the capture stage involves copying the value of the system input to the
core into the serial register. During shift, this value is output serially. The value applied
to the core from an input cell is either the system input or the contents of the serial
register and this is controlled by the multiplexor.
For output cells, capture involves placing the output value of a core into the serial
register. During shift, this value is serially output as before. The value applied to the
system from an output cell is either the core output, or the contents of the serial register.
All of the control signals for the scan cells are generated internally by the TAP
controller. The action of the TAP controller is determined by the current instruction and
the state of the TAP state machine.
There are three basic modes of operation of the scan chains, INTEST, EXTEST, and
SYSTEM that are selected by the various TAP controller instructions:
•
•
System data in
CAPTURE clock
SHIFT clock
SHIFT.
In INTEST mode, the core is internally tested. The data serially scanned in is
applied to the core and the resulting outputs are captured in the output cells and
scanned out.
In EXTEST mode, data is scanned onto the outputs of the core and applied to the
external system. System input data is captured in the input cells and then shifted
out.
Copyright © 1994-2001. All rights reserved.
Serial data out
Serial data in
register
latch
Shift
Figure B-4 Input scan cell
Data to core
Debug in Depth
B-17
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