SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 156
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 156 of 284
- Download datasheet (2Mb)
Instruction Cycle Timings
6.8
6-14
Store register
Cycle
1
2
The first cycle of a store register instruction is similar to the first cycle of load register
instruction. During the second cycle the base modification is performed, and at the same
time the data is written to memory. There is no third cycle.
The cycle timings are listed in Table 6-11 where:
•
•
•
Address
pc+2L
alu
pc+3L
c represents the current processor mode:
—
—
d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at
all other times.
s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on
page 6-13).
Copyright © 1994-2001. All rights reserved.
c=0 for User mode
c=1 for all other modes
MAS[1:0]
i
s
nRW
0
1
Table 6-11 Store register instruction cycle operations
Data
(pc+2L)
Rd
nMREQ
0
0
SEQ
0
0
nOPC
0
1
ARM DDI 0029G
nTRANS
c
d
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