SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 162
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 162 of 284
- Download datasheet (2Mb)
Instruction Cycle Timings
6.13
6-20
CP
status
ready
not ready
Coprocessor data operation
Cycle
1
1
2
•
b
Address
pc+8
pc+12
pc+8
pc+8
pc+8
pc+8
pc+12
A coprocessor data operation is a request from the core for the coprocessor to initiate
some action. The action does not have to be completed for some time, but the
coprocessor must commit to doing it before driving CPB LOW.
If the coprocessor is not capable of performing the requested task, it must leave CPA
and CPB HIGH. If it can do the task, but cannot commit right now, it must drive CPA
LOW but leave CPB HIGH until it can commit. The core busy-waits until CPB goes
LOW.
The cycle timings are listed in Table 6-16 where:
•
Coprocessor data operations are not available in Thumb state.
b represents the busy cycles.
Note
nRW
0
0
0
0
0
Copyright © 1994-2001. All rights reserved.
Table 6-16 Coprocessor data operation instruction cycle operations
MAS
[1:0]
2
2
2
2
2
Data
(pc+8)
(pc+8)
-
-
-
nMREQ
0
1
1
1
0
SEQ
0
0
0
0
0
nOPC
0
0
1
1
1
nCPI
0
0
0
0
0
ARM DDI 0029G
CPA
0
0
0
0
0
CPB
0
1
1
1
0
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