SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 187
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 187 of 284
- Download datasheet (2Mb)
7.12
ARM DDI 0029G
Symbol
T
T
T
T
T
T
abth
abts
im
is
rm
rs
Exception timing
Parameter
ABORT hold time from MCLKf
ABORT set up time to MCLKf
Asynchronous interrupt guaranteed nonrecognition time, with ISYNC=0
Asynchronous interrupt set up time to MCLKf for guaranteed recognition, with ISYNC=0
Reset guaranteed nonrecognition time
Reset setup time to MCLKr for guaranteed recognition
Figure 7-11 shows the ARM7TDMI processor exception timing. The timing parameters
used in Figure 7-11 are listed in Table 7-11.
In Figure 7-11, to guarantee recognition of the asynchronous interrupt (ISYNC=0) or
reset source, the appropriate signals must be setup or held as follows:
•
•
These inputs can be applied fully asynchronously where the exact cycle of recognition
is unimportant.
nRESET
ABORT
MCLK
nIRQ
nFIQ
setup T
hold T
Note
Copyright © 1994-2001. All rights reserved.
im
is
and T
and T
is
rs
respectively after the corresponding clock edge.
respectively before the corresponding clock edge
T
rs
Table 7-11 Exception timing parameters
T
rm
Figure 7-11 Exception timing
T
abts
T
is
AC and DC Parameters
T
T
abth
im
Minimum
Parameter
type
Minimum
Minimum
Maximum
Maximum
Minimum
7-15
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