SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 261
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SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 261 of 290
- Download datasheet (5Mb)
C.7.3
ARM DDI 0165B
Exit from debug state
Leaving debug state involves:
•
•
•
After restoring the internal state, a branch instruction must be loaded into the pipeline.
See Behavior of the program counter during debug on page C-24 for details on
calculating the branch.
The SYSSPEED bit of scan chain 1 forces the ARM9E-S to resynchronize back to CLK
conditioned with CLKEN. The penultimate instruction in the debug sequence is a
branch to the instruction at which execution is to resume. This is scanned in with bit 32
(SYSSPEED) set LOW. The final instruction to be scanned in is a NOP (such as
R0, R0
pipeline.
Next, the RESTART instruction is selected in the TAP controller. When the state
machine enters the RUN-TEST/IDLE state, the scan chain reverts back to System
mode, and clock resynchronization to CLK conditioned with CLKEN occurs within
the ARM9E-S. Normal operation then resumes, with instructions being fetched from
memory.
The delay, waiting until the state machine is in RUN-TEST/IDLE state, allows
conditions to be set up in other devices in a multiprocessor system without taking
immediate effect. Then, when RUN-TEST/IDLE state is entered, all the processors
resume operation simultaneously.
The function of DBGACK is to tell the rest of the system when the ARM9E-S is in
debug state. You can use this signal to inhibit peripherals such as watchdog timers that
have real-time characteristics. Also, you can use DBGACK to mask out memory
accesses that are caused by the debugging process. For example, when the ARM9E-S
enters debug state after a breakpoint, the instruction pipeline contains the breakpointed
instruction plus two other instructions that have been prefetched. On entry to debug
state, the pipeline is flushed. So, on exit from debug state, the pipeline must be refilled
to its previous state. Therefore, because of the debugging process, more memory
accesses occur than are normally expected. It is possible, using the DBGACK signal
and a small amount of external logic, for a peripheral which is sensitive to the number
of memory accesses to return the same result with and without debugging.
You can only use DBGACK in such a way using breakpoints. It does not mask the
correct number of memory accesses after a watchpoint.
restoring the internal state of the ARM9E-S
causing a branch to the next instruction to be executed
synchronizing back to CLK conditioned with CLKEN.
), with bit 32 set HIGH. The core is then clocked to load this instruction into the
Note
Copyright © 2000 ARM Limited. All rights reserved.
Debug in depth
MOV
C-21
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