SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 92
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SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 92 of 290
- Download datasheet (5Mb)
Memory Interface
4.8.3
4.8.4
4-16
DMAS[1:0]
DnTRANS
The DMAS[1:0] bus encodes the size of the transfer. The ARM9E-S can transfer word,
halfword, and byte quantities. This is encoded on DMAS[1:0] as shown in Table 4-8.
The size of transfer does not change during a burst of S cycles. Bursts of halfword or
byte accesses are not possible on the ARM9E-S data interface.
A writable memory system for the ARM9E-S must have individual byte write enables.
Both the C compiler and the ARM debug tool chain (for example, Multi-ICE) assume
that arbitrary bytes in the memory can be written. If individual byte write capability is
not provided, you might not be able to use these tools.
The DnTRANS bus encodes information about the transfer. A memory management
unit uses this signal to determine if an access is from a privileged mode. Therefore, you
can use this signal to implement an access permission scheme. The encoding of
DnTRANS is shown in Table 4-9.
Note
Copyright © 2000 ARM Limited. All rights reserved.
DMAS[1:0]
00
01
10
11
DnTRANS
0
1
Table 4-9 DnTRANS encoding
Table 4-8 Transfer widths
Transfer width
Byte
Halfword
Word
Reserved
Mode
User
Privileged
ARM DDI 0165B
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