SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 94
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SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 94 of 290
- Download datasheet (5Mb)
Memory Interface
4.9
4.9.1
4.9.2
4.9.3
4-18
Data interface data timed signals
WDATA[31:0]
RDATA[31:0]
DABORT
The data timed signals are:
•
•
•
WDATA[31:0] is the write data bus. All data written out from the ARM9E-S is
broadcast on this bus. Data transfers from the ARM9E-S to a coprocessor also use this
bus during C cycles. In normal circumstances, a memory system must sample the
WDATA[31:0] bus on the rising edge of CLK at the end of a write bus cycle. The value
on WDATA[31:0] is valid only during write cycles.
RDATA[31:0] is the read data bus, and is used by the ARM9E-S to fetch data. It is
sampled on the rising edge of CLK at the end of the bus cycle, and is also used during
C cycles to transfer data from a coprocessor to the ARM9E-S.
DABORT indicates that a memory transaction failed to complete successfully.
DABORT is sampled at the end of the bus cycle during active memory cycles (S cycles
and N cycles).
If DABORT is asserted on a data access, it causes the ARM9E-S to take the Data Abort
trap.
DABORT can be used by a memory management system to implement, for example, a
basic memory protection scheme, or a demand-paged virtual memory system.
The ARM9E-S design differs from ARM9TDMI in that ARM9TDMI features a
combinational path from DABORT to DnMREQ, DSEQ, and DMORE. This path is
present so that an aborted memory access can cancel memory accesses requested by
following instructions.
An example of this is shown in Figure 4-5 on page 4-19, where a load instruction
follows an aborted store.
WDATA[31:0]
RDATA[31:0]
DABORT.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
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